Intel Corporation

Jeffrey A Pihlman

Ramamurthy Krithivas

Anand K Enamandram

Amit Kumar Srivastava

Majid Shushtarian

Michael J Karas

Jared W Havican

Christine Watnik

John C Tomlin

Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH. The multi-socket platforms include a platform with a bootable CPU coupled to one or more non-legacy CPUs and employing multiple IO-expanders and platform with a legacy CPU coupled to one or more non-legacy CPUs and coupled to a legacy PCH, and further including one or more PCHs coupled to the non-legacy CPU(s) implemented as IO-expanders.

Platform controller hub (PCH) chipsets in platforms as extended IO expander(s)

Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

Techniques to dynamically enable memory channels on a compute platform

IC device assemblies including a power delivery bus board that is mounted to a primary PCB (i.e., motherboard) that further hosts a power-sink device and a power-source device. The bus board, as a secondary PCB, may be surface-mounted on a back side of the primary PCB opposite the power source and sink devices, which are mounted on the front side of the primary PCB. The bus board need only be dimensioned so as to bridge a length between first and second back-side regions of the primary PCB that are further coupled to a portion of the front-side pads employed by the power-sink device. The secondary PCB may be purpose-built for conveying power between the source and sink devices, and include, for example, short, wide traces, that may be formed from multiple heavyweight metallization layers.

Surface-mountable power delivery bus board

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Steilacoom, WA, United States of America

Jeffrey A Pihlman