Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Jeffrey A Metzger

Barry A Maskas

Nitin Dhiroobhai Godiwala

Kurt M Thaller

Donald W Smelser

Paul M Goodwin

David A Tatosian

George Jerry Harris

Paul J Graffam

A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Bus interface slicing mechanism allowing for a control/data path slice

Bus interface slicing mechanism allowing for a control/data-path slice

The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.

Fault management scheme for a cache memory

The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is operated according to a SNOOPY protocol. The computer apparatus includes a processor and a cache memory coupled to the processor. The cache memory contains a subset of the data items stored in the main memory, for access by the processor and includes a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory. A bus interface is coupled to the cache memory and is adapted for coupling to the bus. The interface operates according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators and determines the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset. The interface operates further to invalidate or update each VALID data item of the subset when there is a write transaction affecting the data item. An invalidate operation includes a clearing of the corresponding VALID indicator for the affected data item by the interface and an update operation includes overwriting of the affected data item by the interface from the write transaction on the bus. The operation of the interface to invalidate or update is performed as a function of the identity of the initiator of the write transaction determined by the interface.

Update vs. invalidate policy for a snoopy bus protocol

The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.

Scheme for error handling in a computer system

A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a backup cache and a bus interface. The backup cache memory a first TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the backup cache memory. The primary cache memory includes a second TAG store comprising a plurality of address indicators and a plurality of VALID indicators, one address indicator and one VALID indicator for each of the data items currently contained in the primary cache memory. The interface includes a duplicate TAG store coupled to the primary cache memory, the duplicate TAG store consisting of a copy of the address indicators of the second TAG store. The bus interface is coupled to the processor, the backup cache memory and to the bus. The bus interface operates in accordance with a SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items in the corresponding backup cache memory having set VALID indicators. The bus interface will invalidate or update each VALID data item of the backup cache memory when there is a write transaction affecting data item and assert an invalidate signal for an affected data item indicated by the address indicators of the duplicate TAG store. The invalidate signal causes the VALID indicator in the second TAG store for the affected data item to be cleared.

Duplicate tag store for a processor having primary and backup cache

A system and method for interconnecting electronic components on a circuit board that minimize etch lines, minimize stub lengths, reduce the number of vias that are needed, and densely pack electronic components on the circuit board. According to system and method, electronic components are attached to the top planar surface of the circuit board such that adjacent components are rotated 180.degree. in the plane of the top planar surface. These adjacent electronic components also are offset from one another. The electronic components that are attached to the bottom planar surface of the circuit board also have adjacent electronic components rotated 180.degree. in the plane of the bottom planar surface, and are offset. The arrangement of the components disposed at the bottom planar surface is a mirror image of the components disposed at the top planar surface.

Interconnect arrangement for electronic components disposed on a circuit

The present invention is a circuit for converting the logic voltage levels from those of a first device to those of a second device. This conversion is accomplished while substantially isolating the second device from the effects of the first device that could influence the outputs of the second device that represent the converted logic level voltages.

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Leominster, MA, United States of America

Jeffrey A Metzger