Texas Instruments Corporation

Jeffrey A McKee

Chih-Chen Cho

Peter S McAnally

Isamu Asano

William R McKee

Srikanth Krishnan

Ming J Hwang

Robert Yung-Hsi Tsu

Troy H Herndon

Jing-Shing Shu

Michael P Keleher

Theodore Warren Houston

Amitava Chatterjee

Somnath S Nag

Keith Alan Joyner

Dirk N Anderson

Ih-Chin Chen

Yin Hu

Iqbal Ali

Jing Shing Shu

Joseph K Russell

Agerico L Esquirel

A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the elongated projection. A gate structure is operable to control the access channel to selectively couple the first terminal to the second terminal.

Gate device with raised channel and method

A method for fabricating a memory array includes fabricating a first portion ( ) of a memory array on a first side ( ) of a substrate ( ). A second portion ( ) of the memory array is fabricated on a second, opposite side ( ) of the substrate ( ). The first portion ( ) and the second portion ( ) of the memory array are coupled to each other through the substrate ( ).

Method for two-sided fabrication of a memory array

An integrated circuit. The circuit includes a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Integrated circuit and method

A mask ( ) includes a pattern ( ) having a plurality of substantially rectangular shapes ( ) arranged longitudinally in each of a plurality of substantially parallel rows ( ). The rows ( ) are evenly spaced apart from each other. The substantially rectangular shapes ( ) in each row ( ) are evenly spaced apart from each other and offset from the substantially rectangular shapes ( ) in neighboring rows ( ). The substantially rectangular shapes ( ) define a plurality of T-shapes ( ) connected to and offset from each other.

Mask and method for forming dynamic random access memory (DRAM) contacts

A method for fabricating a gate device includes forming an elongated projection (,) on a substrate (,). The elongated projection (,) protrudes from a surrounding area (,) of the substrate (,) and includes an access channel (,) for the gate device. A first terminal (,) and a second terminal (,) are formed and coupled to the access channel (,) in the elongated projection. A gate structure (,) is formed and operable to control the access channel (,) to selectively couple the first terminal (,) to the second terminal (,).

Method of forming a gate device with raised channel

A method for fabricating a gate device includes forming a discrete post on a substrate. The discrete post protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the discrete post. A gate structure is formed and operable to control the access channel to selective couple the first terminal to the second terminal.

Gate device with access channel formed in discrete post and method

A chemical mechanical polishing machine with ultrasonic vibration is disclosed. The chemical mechanical polishing machine (,) includes a movable abrasive surface (,). A wafer holder (,) holds a wafer (,) in contact with the abrasive surface (,), and a vibration generator (,) vibrates the wafer (,) during polishing. The ultrasonic vibration agitates the slurry and provides an additional degree of motion between the wafer and the abrasive surface, thereby increasing the speed and uniformity of the polishing.

Chemical mechanical polishing machine with ultrasonic vibration and method

Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (,) over an oxidizable section (,) of the semiconductor device. The protective cover (,) is operable to at least inhibit oxidation of the oxidizable section (,). While the oxidizable section (,) is covered, an oxide structure (,) is formed. The oxide structure (,) is operable to at least ameliorate etch damage to the semiconductor device.

Post-etch treatment of a semiconductor device

A mask (,) includes a pattern (,) having a plurality of substantially rectangular shapes (,) arranged longitudinally in each of a plurality of substantially parallel rows (,). The rows (,) are evenly spaced apart from each other. The substantially rectangular shapes (,) in each row (,) are evenly spaced apart from each other and offset from the substantially rectangular shapes (,) in neighboring rows (,). The substantially rectangular shapes (,) define a plurality of T-shapes (,) connected to and offset from each other.

A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).

Method for enhancing the performance of a contact

A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.

Self-aligned multiple crown storage capacitor and method of formation

A contact (26) to a substrate (12) is formed using a first stopping layer (14), an insulating layer (16), and a second stopping layer (18). The second stopping layer (18) promotes a more accurate and controlled removal of the first stopping layer (14). A self-aligned contact (122) may be formed in a similar manner using a first stopping layer (110), an insulating layer (112), and a second stopping layer (114).

Method for forming a contact to a substrate

A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to 'dishing' that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Reducing non-uniformity in a refill layer thickness for a semiconductor

A technique for quantifying the effect of plasma etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18. Electrical characterization is performed on modified MOS capacitor 40 yielding information about damage to the oxide in peripheral region 24 caused by the plasma etch. Modified MOS capacitor 40 can be used to compare plasma chemistries, detect oxide trenching, detect etchant loading and determine the effect of process hardware changes, for example. It can especially account for oxide loss in tight geometry features and in regimes where optical measurement techniques are unreliable.

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Grapevine, TX, United States of America

Jeffrey A McKee