Ncr Corporation

Jeffrey A Hawkey

Thomas F Heil

Edward A McDonald

David L Simpson

Larry C James

James M Ottinger

Jeffrey F Gates

Carl W Kagy

Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.

Apparatus and method for address translation and allocation for a

System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough. The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. If memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus. To ensure proper operation with such devices, a pacing or ready signal is generated such that access is delayed until the requested access can be successfully completed.

Computer system configuration via test bus

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Easley, SC, United States of America

Jeffrey A Hawkey