Aehr Test Systems, Inc.

Jeffrey A Brehm

Patrick M Shepherd

James F Tomic

John Dinh Hoang

William D Barraclough

Mikhail A Alperin

A system for testing semiconductor devices on device test boards has a single tester channel connected to multiple DUTs in a loop. Outputs from DUTs are received at a comparator and latch after a period of Round Trip Delay (RTD). The comparator is connected in a parallel configuration with the return path of the loop, where the point of connection is in greater proximity to DUT output pins than the test channel and is a path different from the tester I/O driver path, thus preventing input signals from test drivers from interfering with output signals from DUTs that will serve as inputs to test circuitry. The time it takes a new input cycle state to reach the output comparator is long after the output from a prior cycle has been tested. A diode clamp and resistor are connected in a series with the comparator at the input stage near the comparator in order to reduce ringing at the input of the comparator, which limits tester speed. Bus-switches composed of Field Effect Transistors (FET) electrically switch the input/output (I/O) of DUTs being tested to either exclusively drive or receive trace lines, respectively, reducing DUT pin loading and thus increasing achievable testing speed. The improved testing system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

Enhancements in testing devices on burn-in boards

A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

Method and system for testing memory programming devices

A high density interconnect system (30) employs contact fingers (32) on both surfaces (34) and (36) of burn-in PCB (38), feed-through PCB (40) and driver PCB (42). Each of the PCBs (38), (40) and (42) has a card-edge connector (44), (46) and (48). The feed-through PCB (40) has a second card-edge connector (40) and a second set of contact fingers (32), since it mates with both the burn-in PCB (38) and the driver PCB (42). The contact fingers (32) and the card-edge connectors (44), (46), (48) and (50) of each PCB (38), (40) and (42) mate inversely with each other on adjacent PCBs, i.e., the card-edge connector (44) of the burn-in PCB (38) mates with the contact fingers (32) of the feed-through PCB (40), and the card-edge connector (46) of the feed-through PCB (40) mates with the contact fingers (32) of the burn-in PCB (38), for example. The same relationship exists between the card-edge connector (50) of the feed-through PCB (40), the card-edge connector (48) of the driver PCB (42) and the contact fingers (32) of the feed-through PCB(40) and the driver PCB (42).

Growing community of inventors

South San Francisco, CA, United States of America

Jeffrey A Brehm