Allen-bradley Company, LLC

Jeffery W Brooks

Charles Martin Rischar

Ronald Edwin Schultz

Raymond R Husted

Otomar S Schmidt

Richard S Gunsaulus

Michael D Yoke

Amir S Ansari

John J Kolat, Jr

An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.

Integrated relay ladder language, reduced instruction set computer

A compiler for an industrial controller uses a user modifiable instruction table to contain code fragments necessary to compile particular instructions. During compilation, the instructions are replaced with the code fragments. Thus new instructions recognizable by the compiler may be added simply by editing this instruction table. Multiple instructions having the same name are resolved through a best match of operand types which examines the possible data loss in conversion of operand types to select a particular one of the instructions.

Industrial controller compiler with expandable instruction set

A method of handling a fault which occurs during execution of an executable program comprises the steps of designating a first sequence of instructions of the executable program as visible and designating a second sequence of instructions of the executable program as invisible. According to this scheme, for the first visible sequence of instructions, faults are reported in a manner which designates an instruction at which the fault occurred. For the second invisible sequence of instructions, faults are reported in a manner which designates the invisible sequence of instructions as a whole. The invention permits fault handling for instructions added by a user to be performed in the same way as fault handling for built-in functions, and is usable with compiled machines.

Fault handling with loaded functions

A machine is operated by a programmable controller that executes a ladder logic control program. A custom ladder logic processor is provided for high speed execution of the more common ladder logic instructions and a microprocessor interprets the remaining ladder logic instructions. A first section of memory contains a ladder logic control program in which some of the instructions are macro instructions executable by the ladder logic processor. Each macro instruction specifies an operation code, a first memory file containing data to be processed by the macro instruction, a second memory file containing control data governing the processing, and a storage location for results produced by execution of the macro instruction. Another memory section stores a library file containing a ladder logic software routine for each macro instruction, and stores a directory which identifies a starting location of the macro instruction routine for each operation code. When a macro instruction is encountered in the control program, the corresponding ladder logic software routine is executed. During the execution of the routine data is obtained from the first memory file and the results are placed in the storage location. At the completion of the ladder logic software routine, execution of the control program resumes.

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Mentor-On-The-Lake, OH, United States of America

Jeffery W Brooks