Cypress Semiconductor Corporation

Camgian Microsystems Corp.

Jeffery Scott Hunt

Satish C Saripella

George M Ansel

Ajay Srikrishna

Muthukumar Nagarajan

David Robert Lindley

Sudhaker Reddy Anumula

Brian P Evans

Andrew L Hawkins

Christopher W Jones

Daniel Eric Cress

Jeffery Mark Marshall

Derrick J Savage

Gary Butler

Hatem Yazbek

Hagop A Nazarian

Anup Nayak

Lin-Shih Liu

Stephen M Douglass

Andrew J Wright

Syed B Raza

Sanjay K Sancheti

William G Baker

Jeffrey William Waldrip

Scott Anthony Jackson

Junfei Fan

James Daniel Merchant

Gordon Carskadon

Sanjay Sunder

Jun Li

Anand K Chamakura

Michael David Fliesler

Morgan Andrew Whately

Ping Wu

Suwei Chen

Kalyana C Vullaganti

Vinod Rajan

Benjamin J Bowers

David A Lindley

Muthu Nagarajan

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Multiple sensor data processor interface and relay

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner. Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting

Disclosed is a circuit comprising an inverter circuit which comprises inverters and level shifters; and a modulation circuit comprising a pull-up circuit and a pull-down circuit, the modulation circuit coupled to the inverter circuit to regulate the response of the circuit to an input voltage for various power supply voltage levels by the pull-up or pull-down circuit. Other embodiments are also disclosed.

Input buffer with adaptive trip point

A variable impedance sense (VIS) circuit () can detect and store an input offset value inherent in a sensing loop (and/or). According to a detected input offset polarity, a resulting impedance matching binary code can be adjusted to compensate for error that can be introduced by the input offset. The binary code can also be adjusted to compensate for additional error that can be introduced by dropping a least significant bit (LSB) of the code to reduce noise effects caused by the switching of the LSB.

Variable impedance sense architecture and method

An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

Configurable matrix architecture

A data path () can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path () can be compact circuit structure, needing only an additional mode multiplexer () and inverter over a conventional D-type master-slave flip-flop.

Data path configurable for multiple clocking arrangements

A multi-port memory cell () can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell () can be cleared by shorting complementary data nodes (-and-) together. Write data can then be placed on a bit line. Complementary data nodes (-and-) can then be isolated once again, resulting in the write data being latched within the memory cell (). An access method () for a multi-port memory cell is also described.

Multi-port memory cell and access method

A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy

An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.

Push/pull multiplexer bit

A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.

Buffer circuit using low voltage transistors and level shifters

An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

Input buffer system using low voltage transistors

An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.

Layout architecture to optimize path delays

An apparatus comprising a first compare circuit, a second compare circuit and a memory. The first compare circuit may be configured to present a first match signal in response to a first address and a second address. The second compare circuit may be configured to present a second match signal in response to the first match signal, a first write enable signal and a second write enable signal. The memory may also be configured to present the first and second write enable signals. In one example, the memory may be configured to store and retrieve data with zero waiting cycles in response to the second match signal.

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Ackerman, MS, United States of America

Jeffery Scott Hunt