Hamilton Sundstrand Corporation

Jeffery S Schmidt

Tyler W Hayes

Kamaraj Thangavelu

An aircraft includes an electrical system and an electronic controller. The electronic controller includes a main processor and a multi-core processor. The multi-core processor includes a control core in signal communication with the electrical system, and one or more prognostics cores configured to process and analyze prognostics and diagnostics data of the electrical system independently from operation of the control core. A wireless device is in signal communication with one or more of the prognostics cores to receive the prognostics and diagnostics data therefrom. The aircraft further includes a prognostics and health monitoring (PHM) system located remotely from the electronic controller. The PHM system is configured to wirelessly receive the prognostics and diagnostics data from the wireless device.

Aircraft controller including multiple core processor with wireless transmission prognostic/diagnostic data capability

An aircraft includes an electrical system and an electronic controller in signal communication with the electrical system. The electronic controller including a main processor and a multi-core processor. The multi-core processor includes one or more control cores and one or more prognostic cores. The control core is in signal communication with the electrical system to control power delivered thereto. The prognostics core is configured to process prognostics and diagnostics data of the electrical system independently from operation of the control core.

Multiple core motor controller processor with embedded prognostic/diagnostic capabilities

An example method for uninterrupted execution of control software in an aircraft control system includes creating a plurality of static data copies. A first parity bit is determined for each of the plurality of static data copies. A second parity bit is determined for a first static data copy. A parity fault is detected in the first static data copy if the first parity bit does not match the second parity bit. The system switches to read a second static data copy in response to detecting a parity fault in the first static data copy.

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Rockton, IL, United States of America

Jeffery S Schmidt