Intel Corporation

Jeffery S Boles

Altug Koker

Joydeep Ray

Abhishek R Appu

Balaji Vembu

Prasoonkumar Surti

Adam T Lake

Travis T Schluessler

Michael Apodaca

John H Feit

Hema Chand Nalluri

Karthik Vaidyanathan

Jonathan Kennedy

Murali Ramadoss

Subramaniam M Maiyuran

Kamal Sinha

Ankur N Shah

Kai Xiao

Devan Burke

Jacek Kwiatkowski

Wenyin Fu

Ben J Ashbaugh

Chandrasekaran Sakthivel

Narayan Srinivasa

Justin E Gottschlich

Feng Chen

Nikos Kaburlasos

Eriko Nurvitadhi

Linda L Hurd

Sara S Baghsorkhi

Nicolas C Galoppo Von Borries

Rajkishore Barik

Dukhwan Kim

Nadathur Rajagopalan Satish

James M Holland

Tsung-Han Lin

Josh B Mastronarde

Farshad Akhbari

Elmoustapha Ould-Ahmed-Vall

Atsuo Kuwahara

Aditya Navale

Gabor Liktor

Slawomir Grajewski

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Louis Feng

Mayuresh M Varerkar

Deepak Shashidhar Vembar

Radhakrishnan Venkataraman

Vasanth Ranganathan

Peter L Doyle

James A Valerio

David M Cimini

Lalit K Saptarshi

Hugues Labbe

Pattabhiraman K

Bhushan M Borole

Philip R Laws

Brent E Insko

Eric J Hoekstra

Sayan Lahiri

Anupreet S Kalra

Abhishek Venkatesh

Sameer Kp

Andrew T Lauritzen

Brandon L Fliflet

Joseph Koston

Rahul A Kulkarni

David M Puffer

Aravindh V Anantaraman

Niranjan L Cooray

Arthur Hunter, Jr

Srinivasan Embar Raghukrishnan

Anirban Kundu

Rahul Vijay Kulkarni

Jeffrey S Frizzell

Kritika Bala

Pritav Shah

Hughes Labbe

Arthur D Hunter Jr

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

Sensory enhanced augmented reality and virtual reality device

Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

Dynamic load balancing of compute assets among different compute contexts

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

Cloud based distributed single game calculation of shared computational work for multiple cloud gaming client devices

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Order independent asynchronous compute and streaming for graphics

An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

Collaborative multi-user virtual reality

Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

Augmented reality and virtual reality feedback enhancement system, apparatus and method

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of processing cores of a first type and a second type. A first set of processing cores of a first type perform multi-dimensional matrix operations and a second set of processing cores of a second type perform general purpose graphics processing unit (GPGPU) operations.

Growing community of inventors

Folsom, CA, United States of America

Jeffery S Boles