Qorvo Us, Inc.

Rf Micro Devices, Inc.

Motorola Corporation

Jeffery Peter Ortiz

Alexander Wayne Hietala

Marcus Granger-Jones

Michael R Kay

Scott R Humphreys

David Halchin

Jin D Kim

Jinsung Choi

Jackie Johnson

Timothy Keith Coffman

Wendel Charles

Yan Li

A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.

SPDT switches with embedded attenuators

A radio frequency (RF) power detector is disclosed. The RF power detector includes an envelope detector having an RF signal terminal and a current mode terminal, wherein the envelope detector is configured to detect peak voltages of an RF signal at the RF signal terminal. Further included is a detector current mirror having a first mirror branch coupled to the current mode terminal and a second mirror branch configured to create a detector current that is proportional to a branch current through the first mirror branch in response to peak voltages detected by the envelope detector.

Radio frequency power detector

A differential power amplifier having first and second amplifiers with first and second signal output terminals along with bias circuitry in communication with the first and second amplifiers is disclosed. The differential amplifier further includes a first output clamp coupled to the first signal output terminal and a bias control terminal of the bias circuitry, wherein the first output clamp is configured to limit voltage at the first signal output terminal to a first predetermined voltage magnitude and lower bias current to the first amplifier in response to an overvoltage at the first signal output terminal. A second output clamp is coupled to the second signal output terminal and is configured to limit voltage at the second signal output terminal to a second predetermined voltage magnitude.

Differential power amplifier

A differential power amplifier is disclosed. The differential power amplifier includes an output transformer having a primary winding with a first primary terminal, a center-tap terminal, and a second primary terminal. The differential power amplifier further includes a positive amplifier having a first signal output terminal coupled to the first primary terminal and a negative amplifier having a second signal output terminal coupled to the second primary terminal. A harmonic tuning network is made up of a common-mode inductor coupled between the center-tap terminal and a tuning node and a first electronically tunable capacitor coupled between the tuning node and a fixed voltage node. A controller is configured to tune the electronically tunable capacitor to resonate with the common-mode inductor at a second harmonic frequency of a signal being amplified by the positive amplifier and the negative amplifier.

An output matching network for a differential power amplifier comprises an output transformer having a center tap and a low pass filter. The output transformer is configured to receive a first amplified signal from a first differential output stage amplifier of the differential power amplifier and provide a first output signal to the low pass filter. The output transformer is also configured to receive a second amplified signal from a second differential output stage amplifier of the differential power amplifier and provide a second output signal to the low pass filter. The low pass filter is configured to receive the first and second output signal from the output transformer and provide a filtered output signal.

Output matching network for differential power amplifier

A differential power amplifier has at least an input stage and an output stage. A first output stage amplifier is configured to receive a first portion of a differential signal from the input stage at a first output stage input and provide a first amplified signal at a first output stage output. The second output stage amplifier is configured to receive a second portion of the differential signal from the input stage at a second output stage input and provide a second amplified signal at a second output stage output. Power limiter circuitry is connected to the first and/or output stage inputs and is configured to limit a power level of the differential signal prior to being received at the output stage, such that the differential power amplifier and associated filters are not damaged, while the nominal performance of the differential power amplifier at rated power is not significantly affected.

Multistage differential power amplifier having interstage power limiter

A differential power amplifier comprises an envelope tracking power supply configured to provide an envelope power supply signal to the differential power amplifier. The differential power amplifier also comprises an input stage configured to provide a differential signal having a first portion and a second portion to a differential output stage. The differential output stage comprises a first output stage amplifier configured to receive the first portion of the differential signal at a first output stage input and provide a first amplified signal at a first output stage output, as well as a second output stage amplifier configured to receive the second portion of the differential signal at a second output stage input and provide a second amplified signal at a second output stage output. The envelope power supply signal provides power for amplification.

Differential power amplifier for mobile cellular envelope tracking

Multimode radio frequency (RF) amplifier systems and techniques are disclosed. In one embodiment, a multimode radio frequency (RF) amplifier system has a first RF amplifier and a second RF amplifier. The first RF amplifier may support a first RF communication standard. The second RF amplifier may support a second RF communication standard. The first RF amplifier includes an auxiliary circuit. The auxiliary circuit may provide a service or a utility to a second RF amplifier. For example, the auxiliary circuit may generate a supply voltage to power the second RF amplifier.

Multimode RF amplifier system

Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.

Multimode differential amplifier biasing system

In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system.

Voltage, current, and saturation prevention

A circuit and method for a saturation correction of a power amplifier (PA) is provided in order to maintain a desirable switching spectrum. The circuit includes a closed loop system that is responsive to a dynamic PA control signal known as V. The method samples a detector voltage that represents the output of the PA at the maximum voltage level of V. The sampled detector voltage is then reduced by a predetermined amount and applied as a fixed voltage PA control signal in the place of V. As a result, the closed loop system responds to the fixed voltage PA control signal to bring the PA out of saturation before Vcan begin a voltage decrease. Once the Vvoltage decreases, Vis reapplied as a dynamic PA control signal in place of the fixed voltage control signal.

Saturation correction without using saturation detection and saturation prevention for a power amplifier

The described devices, systems and methods include an integrator circuit having two separate operational modes to control a power output level delivered by the power amplifier to an antenna during start of a transmission burst. The first operational mode utilizes a wide bandwidth control loop to pre-charge a capacitor of the integrator circuit, which generates a pedestal voltage delivered to the power amplifier control input. The second operational mode utilizes a lower bandwidth control loop to ensure stable operation of the control loop during normal operation of the power amplifier.

Pre-charge of a power amplifier pedestal voltage

A dual FET detector having a common RF input and a common detector output for two detector circuits is provided. The first detector circuit is optimized for detecting lower RF signal levels while the second detector circuit is optimized for detecting higher RF signal levels. A detector output voltage output from the common detector output is a composite signal made up of the individual contributions of the two detector circuits. A control circuit receives a feedback signal derived from the detector output voltage, and uses the feedback signal to control a transition between urging a predominance of the contribution to the detector output voltage from one of the detector circuits to the other. The control of the transition between the detector circuits ensures that whichever of the two detector circuits is best optimized for a particular RF signal level will contribute the most to the detector output voltage.

Dual FET detector

A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.

System and method for transitioning from one PLL feedback source to another

A resistor network bias circuit (24) and method is suitable for use in monolithic circuits. The method involves selecting resistors set a quiescent current for a two-stage power amplifier. The bias circuit (24) offsets the gate voltage for a first transistor (14) and a second N-channel depletion mode MESFET transistor (22) to maintain substantially constant drain current for the power amplifier over a range of threshold voltages. Selectable metal links (33-83) serially connected to resistors (30-80) provide parallel resistor combinations (36-86) for setting the quiescent currents of transistors (14 and 22).

Growing community of inventors

Chandler, AZ, United States of America

Jeffery Peter Ortiz