Qualcomm Incorporated

Nvidia Corporation

Qualcomm Connected Experience, Inc.

Jeffery Michael Schottmiller

Rodney Wayne Smith

Michael Scott McIlvaine

Brian Stempel

Melinda Joyce Brown

Andrew S Irwin

James Norris Dieffenderfer

Michael W Morrow

Michael Alan Fetterman

Robert Ohannessian

Manan Patel

Daren Eugene Streett

Yusuf Cagatay Tekmen

Luke Yen

Kiran Ravi Seth

Ming Liang Milton Lei

Praveen Kaushik

Pritha Ghoshal

Tejaswi Talluru

Daniel Higdon

Brian Michael Stempel

Michael Scott Mcilvaine

Michael William Morrow

Daniel S Higdon

Kulin Narendra Kothari

A first instruction to load a first data into a first register file associated with a first subpartition unit is received. A second instruction to load the first data into a second register file associated with a second subpartition unit is received. The first instruction and the second instruction are coalesced into a first entry of a request coalescer based on instruction identifiers. The first entry is associated with the first data. Responsive to a determination that the first data is available in the cache, the first data is multicast from the cache to the first register file and the second register file.

Systems and methods for multicasting data

A method for speeding the re-use of Physical Register Names (PRNs), and hence the processor registers, in a processor. The method involves returning a PRN to a freelist for reuse when it is obsolete even when it is not complete, and blocking writes to the Processor Register File (PRF) by obsolete realms.

Fast reuse of physical register names

An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.

Method to improve speed of executing return branch instructions in a processor

Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Growing community of inventors

Raleigh, NC, United States of America

Jeffery Michael Schottmiller