Vlsi Technology, Inc.

Cirrus Logic Inc.

Intel Corporation

S3 Incorporated, Inc.

Jeffery M Michelsen

Gary D Hicok

Joseph Alan Thomsen

Ned D Garinger

Mitchell A Stones

Clark T Woolsey

A virtual memory manager for a multi-media engine allows individual media units to operate in their own virtual space in much the same way as a software program operating in virtual mode. The virtual memory controller performs address translation or mapping to the correct physical memory location (in local memory or system memory) and will also convert the data stream to or from a compressed format. In addition, the virtual memory controller provides a unified TLB (translation lookaside buffer) available to all media units. The TLB has four types of pointer entries which are controlled by two bits. The first bit controls whether the TLB entry is a direct map or a pointer to another translation table. the second bit controls whether the TLB entry is stored in a compressed format. The overall concept may allow dynamic load balancing between local media memory and system memory.

Memory manager for multi-media apparatus and method therefor

One embodiment of a graphics device that can be disabled when an upgrade graphics device is installed is described. The graphics device includes an interface to a bus and an input to receive a device disable signal. When the device disable signal is asserted, the interface to the bus places its buffers in a high impedance state, meaning that the graphics device is electrically isolated from the bus. When the device disable signal transitions from asserted to deasserted, a reset circuit in the graphics device resets the graphics device.

Method and apparatus for disabling a graphics device when an upgrade device is installed

A programmable filter is provided for filtering image or texture map data. A weighting RAM stores weighting data for filtering data in both x and y directions. Different weighting values may be programmed into weighting RAMs to provide different weighting functions and also enable or disable a number of taps within the filter. A weighting value of zero, for example, may disable a particular tap for the filter. In the preferred embodiment, a number of lines in the x direction may be simultaneously weighted and then weighted and combined in the y direction to produce a filtered value within one clock cycle.

Programmable four-tap texture filter

A compositing buffer having an adjustable size and configuration reduces complexity and size of a multimedia processor integrated circuit. The compositing buffer may be optimized for lower resolutions, thus reducing its overall size and complexity, while still providing support for higher resolutions which may be required to support a particular standard. A pixel mapping logic receives data indicating the number of lines per band and number of pixels per line, as well as color depth (or any two of these data) and correctly maps compositing RAM bank access requests to the correct pixel location. In a second embodiment of the present invention, the variable band size of the compositing buffer may allow for an external memory to be used for a compositing buffer, for example, a portion of the display memory (frame buffer). While such an embodiment may reduce overall bandwidth, the associated cost reduction may make such an apparatus appealing for low cost applications. Band size may be adjusted depending upon pixel resolution and depth. In a third embodiment of the present invention, band size may be varied within a frame depending upon the number of layers or the complexity of each image portion. Simple portions of an image, have few layers, may be rendered using wide bands, whereas complex areas may be rendered in narrower bands.

Variable band size compositing buffer method and apparatus

CPU system performance is improved by reducing the time required to complete a DRAM access by microprocessors such as the 386DX, 386SX and 80286 by incorporating a programmable DRAM controller therewith which permits consecutive DRAM accesses to average N+0.5 processor wait states. The half wait state average is obtained by forcing the system CPU to measure wait states in processor clock time units which are twice the period of an independent clock in the DRAM controller which, in turn, triggers RAS and CAS assert and de-assert. RAS or CAS is thus able to assert 1/2 processor clock period earlier in one memory cycle relative to the last. Early assert time also provides for an early de-assert time so that data can be transferred to/from the DRAM more quickly than previously possible.

N+0.5 wait state programmable DRAM controller

A microchip circuit for use in and method for use with PC/AT microprocessor environments enables both local memory and ISA bus memory to be refreshed while reducing CPU overhead time entailed in a performing refresh by providing decoupled refresh cycles for the local memory and the ISA memory.

Decoupled refresh on local and system busses in a PC/at or similar

A variable drive output buffer circuit for use to drive memory address lines, or the like, in a computer system has the drive output connected in parallel to a group of output buffer drive circuits, each of which is supplied with the drive signal. Each of the output buffer drive circuits, preferably in the form of CMOS buffer circuits, is selectively individually enabled or disabled to select the optimum number of output drive circuits which are operated in parallel to supply the drive signal to the output bonding pad. All of the disabled drive circuits are placed in a high impedance state, so that they essentially are removed from the circuit and do not affect the total drive capability.

Growing community of inventors

Mesa, AZ, United States of America

Jeffery M Michelsen