Intel Corporation

Jeffery L Krieger

Christopher P Mozak

Inder M Sodhi

Shaun M Conrad

Philip R Lehwalder

Xiuting C Man

Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (V) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

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Portland, OR, United States of America

Jeffery L Krieger