International Business Machines Corporation

Jeffery Howard Oppold

Michael Richard Ouellette

Randy William Mann

Chung H Lam

Jeffrey Scott Brown

Michael Thomas Fragano

Neelesh Govindaraya Pai

John Atkinson Fifield

James Norris Dieffenderfer

Joel Abraham Silberman

Stephen Victor Kosonocky

Norman Jay Rohrer

Thomas Philip Speier

William Robert Reohr

Steven Frederick Oakland

David E Lackey

Francois Ibrahim Atallah

Paul David Kartschoke

Ram Kelkar

Stephen Dale Wyatt

William A Klaasen

Ilya I Novof

Jeffrey Herbert Fischer

Larry Wissel

Thomas Gregory Sopchak

Steven Michael Eustis

Pamela Sue Gillis

Michael J Sullivan

Jeremy Paul Rowland

Thomas R Bednar

Jonathan R Fales

John A Gabric

Leah Marie Pfeifer Pastel

Muthukumarasamy Karthikeyan

Richard F Keil

Kenneth Dean Short

James A Svarczkopf

Adam G Moldovan

Daved J Wager

Daniel Stephen Geise

A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Dense register array for enabling scan out observation of both L1 and L2 latches

The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.

Efficient circuit and method to measure resistance thresholds

A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.

Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines

A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.

Detector for alpha particle or cosmic ray

A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.

Diagnosable scan chain

A zero threshold voltage (ZVt) pFET () and a method of making the same. The ZVt pFET is made by implanting a p-type substrate () with a retrograde n-well () so that a pocket () of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask () having a pocket-masking region () in the aperture () corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well () and then annealing the substrate so as to cause the regions of the lower portion () of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (), gate (), source (), and drain ().

Zero threshold voltage pFET and method of making same

A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a 'don't care' state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

Redundancy register architecture for soft-error tolerance and methods of making the same

A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.

Random access memory having an adaptable latency

A zero threshold voltage (ZVt) pFET ( ) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate ( ) with a retrograde n-well ( ) so that a pocket ( ) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask ( ) having a pocket-masking region ( ) in the aperture ( ) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well ( &prime;) and then annealing the substrate so as to cause the regions of the lower portion ( &prime;) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator ( ), gate ( ), source ( ), and drain ( ).

Zero Threshold Voltage pFET and method of making same

A testing method and device for detecting the existence of &ldquo;stuck-open&rdquo;, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.

Self-Test pattern to detect stuck open faults

A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.

Performance optimizing compiler for building a compiled SRAM

A precharge wordline decoder is disclosed that comprises a first logic circuit that receives a first clock signal from a clock driver for enabling the discharge element within the first logic circuit. The wordline decoder further comprises a delay circuit for generating a predetermined delayed clock signal from the first clock signal, the delayed clock signal being locally-controlled. A second logic circuit of the wordline decoder receives the delayed clock signal for controlling wordline driver elements. The first logic circuit also receives the delayed clock signal for disabling the precharge elements of the decoder.

Precharged wordline decoder with locally-controlled clock

An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor. This second layer of metal may also be used to form inductors. Moreover both inductors and resistors can be formed; however this may require a third layer of metal for connection purposes.

Integrated compact capacitor-resistor/inductor configuration

Growing community of inventors

Richmond, VT, United States of America

Jeffery Howard Oppold