Xilinx, Inc.

Quantum Corporation

Jeffery H Appelbaum

Ahmad R Ansari

Kam-Wing Li

James J Murray

John Welsford Brooks

Alex Scott Warshofsky

Kathryn Story Purcell

Richard J Blackborow

Tim R Glassburn

Kunal Ramachandra Shenoy

Farrokh Mottahedin

Eric Kvamme

Faheem Dani

Garrick Yeung

A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Crossbar switch device for a processor block core

A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller. Additional or other interfaces may be coupled to the crossbar interconnect.

Processor block ASIC core for embedding in an integrated circuit

A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Processor local bus bridge for an embedded processor block core in an integrated circuit

Command translation of burst commands is described. A slave processor local bus ('PLB') bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Translation of commands in an interconnection of an embedded processor block core in an integrated circuit

A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host. After all data words have been transferred, the strobe signal is returned to a high state so that it is ready to be used for another host command. By reducing the hold time of the receiving device and controlling the hold time of the sending device, the method reduces timing delays and provides a data transfer rate up to 66.7 MBytes/sec. The method is easily implemented in existing systems and is backward compatible with existing transfer protocols.

System for increasing data transfer rate using sychronous DMA transfer protocol by reducing a timing delay at both sending and receiving devices

A mass storage subsystem is connectable to a host computer via a host adapter and includes a subsystem bus extending from the host adapter to at least one base unit and a removable disk drive cartridge for use with the base unit. A control signal path extends between the base unit and the removable disk drive cartridge when it is installed and connected within the base unit. The disk drive cartridge includes a housing, at least one storage disk rotatably mounted within the housing, at least one data transducer head within the housing and positionable by a head positioner at selected concentric data storage tracks defined on a storage surface of the storage disk. A bus interface circuit is provided for directly connecting to the subsystem bus when the cartridge is installed and connected within the base unit, and a cartridge controller is provided for controlling operations of the bus interface circuit and the head positioner and for communicating with the base unit via the control signal path. The base unit comprises a disk cartridge receiving structure for receiving and connecting the disk drive cartridge, a stand-in interface circuit connected to the subsystem bus means for presenting an active and 'drive not ready' disk cartridge appearance to the subsystem bus when the disk drive cartridge is not installed and connected within the base unit, and a base unit controller including a cartridge control for controlling operations of the disk cartridge receiving structure, and a stand-in interface control for communicating with the cartridge controller via the control signal path and for thereupon controlling stand-in operation of the stand-in interface circuit.

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San Mateo, CA, United States of America

Jeffery H Appelbaum