Ramtron International Corporation

Hitachi, Ltd.

Jeffery E Downs

Michael W Yeager

Yoshihiko Yasu

Gregory M Smith

A single integrated circuit for an RF/ID transponder includes a nonvolatile memory portion, which is ideally a ferroelectric memory, digital logic, digital interface circuitry, and differential analog driver circuitry for driving an antenna that is contained within the RF/ID transponder, but external to the integrated circuit. In series with each leg of the differential analog driver circuitry, and also fabricated on the single integrated circuit, are two groups of serially connected resistors. All circuit nodes associated with the resistors are connected to a signal level control logic block that is in communication with the on-chip digital logic block. The signal level control logic block is used to selectively control the output resistance of the driver circuitry such that a proper balance between incoming and outgoing signal levels is achieved. The output resistance can be programmed to several different levels, the granularity of the levels being determined by the number of serially connected resistors used. An optimum code corresponding to the optimum output resistance is stored in a small portion of the on-chip nonvolatile memory. The code can be externally programmed and updated as required by new applications. The code can also be externally programmed to permanently disable the RF/ID transponder by setting the output resistance to an extremely high level or by open circuiting the output resistance altogether.

Programmable output devices for controlling signal levels in an RF/ID

A data processor incorporating a memory array which is selectably configurable as either read/write or read only memory or the combination of both read/write and read only memory includes a memory mapper for receiving logical addresses from an arithmetic logic unit ('ALU') and converting the same to physical addresses within the memory array in accordance with configuration instructions stored in a local non-volatile memory. By utilizing a common memory technology for the memory array, such as non-volatile ferroelectric random access memory ('FRAM'), the proportions and layout of the memory array which may be utilized for MPU instructions and data may be selectably controlled. The use of a memory mapper also allows for the establishment of an effective password or encryption protection function for the memory array data of particular utility in conjunction with radio frequency identification ('RF/ID') transponders and other applications which must store sensitive data in non-volatile storage.

Data processor incorporating a ferroelectric memory array selectably

A system and method for selective write protection for a non-volatile memory device which comprises a superset of the existing JEDEC 21-C standard and in which user definable portions of a non-volatile memory device can be write protected instead of only the entire device. The write-protection technique of the present invention can be selectably enabled or disabled dynamically as determined by a user. Moreover, the system and method of the present invention provides for storage of the device write-protection configuration in non-volatile memory in order that the device can be restored to its last known write-protection state in the event it is powered down or the current configuration is otherwise lost.

Sysyem and method providing selective write protection for individual

A system and method wherein a predetermined soft fuse value may be written to a corresponding soft fuse register to control subsequent access to a number of lock bits in a non-volatile semiconductor memory array which are provided for selectively precluding writes to predetermined portions of the memory array. In a specific embodiment, the system and method may be utilized in conjunction with radio frequency ('RF') identification ('ID') transponders incorporating a non-volatile ferroelectric random access memory ('FRAM') array integrated circuit.

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Colorado Springs, CO, United States of America

Jeffery E Downs