International Business Machines Corporation

Other

Jeffery Dean Carr

John Michael Sutton

Agnes Yee Ngai

Chuck Hong Ngai

Ronald S Svec

Charles John Stein

A movable pullout step attachable to a vehicle and which has a spring actuated latching mechanism that selectively allows and restrains positioning of the pullout step in either a retracted position under the vehicle or a step position wherein a tread extends away from the vehicle to allow a person to stand thereon to facilitate the access to desired portions of the vehicle.

Pullout step for vehicles

A memory controller utilizing a performance monitor to modulate the level of data security applied to the data being transferred to and from memory depending on the performance. The performance monitor tracks the response time for access to the memory over a defined time window. The response times are then compared to a predefined allowable response time. This comparison is done over a predefined window of time. When the actual response times exceed the allowable limits, the level of encryption is limited until performance parameters fall within the limits selected. The frequency with which the encryption mechanism is adjusted may also be predefined. Data transfers continue as the controller monitors system performance and controls the level of security applied to the data according to that performance data. The performance modulation can be different depending on what unit is accessing memory in multi-unit systems.

Memory controller with performance-modulated security

A method and apparatus are provided for implementing seamless error resumption in a shared memory bus structure. Controls and data are stored for each read operation and each write operation. Each read operation and each write operation is monitored to determine when an error has occurred for either a read operation or a write operation. When an error has occurred for the read operation or the write operation, the error is suppressed and the stored controls and data are gated to continue the read operation or the write operation.

Method and intelligent slave device transfer control unit for implementing seamless error resumption in a shared memory bus structure

A memory controller, method and program product for memory controller optimization by active re-prioritization of requests based on memory bus activity. The invention continually monitors memory bus activity and, where necessary, re-prioritizes a queue of pending memory requests. In addition, mechanisms are provided to abort an existing request on a memory bus, and interrupt an existing request to complete a pending request.

Memory controller optimization

A data transfer engine, method and article of manufacture are provided for use in a functional unit of an integrated system for enhanced access and transfer of data over a shared data bus. The data transfer technique comprises pipelining data transfer requests onto the shared bus. The technique involves receiving and storing a first transfer parameter set in a primary parameter register within the data transfer structure, and receiving and storing a second transfer parameter set in a secondary parameter register within the transfer structure. Thereafter, data is transferred using the shared memory bus in response to the first transfer parameter set and the second transfer parameter set without relinquishing access to the shared memory bus between transferring of data in response to the different parameter sets. A situational wait decision is preferably implemented in practice to decide whether to pipeline consecutive data transfer requests based upon the characteristics of the first transfer parameter set and/or the second transfer parameter set, as well as the identities of the requesters providing the first transfer parameter set and the second transfer parameter set.

Data transfer method/engine for pipelining shared memory bus accesses

An MPEG-2 compliant digital video encoder system having a refinement processor for reconstructive processing for I-picture and P-picture encoding. The refinement processor includes a frame difference unit which has a predicted error array (PE array). The predicted error array comprises a shared-use array for storing both luminance data and chrominance data of a macroblock of data. The predicted error array also comprises a dual-port structure and array read control logic which allows simultaneous reading and writing of data to the array. Address selector logic controls addressing of the PE array such that writing of luminance data and chrominance data to the PE array and reading of luminance data and chrominance data from the array remains synchronous.

Control scheme for shared-use dual-port predicted error array

Method and apparatus for encoding digital motion video where a motion vector is formed to describe the translation of a set of picture elements from one picture to another. This is accomplished by calculating a difference or prediction error between a current luminance macroblock and a best match reference luminance macroblock, and between a current chrominance macroblock and a best match reference chrominance macroblock. This is done by selecting a chrominance prediction mode from among a set of chrominance prediction modes. Using the selected chrominance prediction mode, a full or half pel interpolation is calculated and from this a difference or prediction error is calculated between a current chrominance macroblock and a best match reference chrominance macroblock. The required reference chrominance data is fetched, and a chrominance difference or prediction error is calculated. The output is the chrominance difference or prediction error data.

Optimized field-frame prediction error calculation method and apparatus

An MPEG digital video decoder system, method and computer program product are presented for monitoring decoding of an encoded digital video signal for one or more predefined illegal conditions. Error detection logic is coupled to the variable length (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transformer (IDCT) and motion compensator (MC) of the decoder for detecting an illegal condition within at least one of the VLC decoder, IQ, IDCT and MC during decoding of the encoded digital video signal. The monitored illegal conditions can include a VLC/IQ control error, an IQ level overrun, and IQ/IDCT buffer error, an MC idle error and an MC macroblock start error. Error signals are reported to a central error register which is monitored periodically by the decoder's control processor. The control processor initiates recovery within the decoder system prior to stoppage of the system due to the illegal condition.

Early error detection within an MPEG decoder

A scalable architecture MPEG2 compliant digital video encoder system having an I-frame video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. The system also includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element for motion estimation. According to the invention, the difference data between the current macroblock and the reference macroblock is stored, which may be of different formats, is storted in memory in a common format by blocking bits in an address counter of the memory.

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Vestal, NY, United States of America

Jeffery Dean Carr