Taiwan Semiconductor Manufacturing Comp. Ltd.

Jeffery Chu

Hsueh-Liang Chou

Tzu-Yang Wu

Ya-Wen Lee

Chia-Hung Kao

Sheng-Chieh Liu

A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

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Taipei, Taiwan

Jeffery Chu