Cisco Technology, Inc.

Jeffery B Scott

John William Marshall

Scott Nellenbach

Darren R Kerr

Kenneth Harvey Potter, Jr

David Richard Barach

Robert E Jeter, Jr

John Mitten

Kent H Hoult

Christopher G Riedle

Michael L Wright

Kenneth H Potter

Kenneth Michael Key

Barry Scott Burns

Vinayak K Parameshwara

A technique modifies data transferred from a source to a destination on an intermediate node in a network. According to the technique, a processor of the node issues commands to modify the data. The commands are held in a data structure and not performed on the data until the data is transferred from the source to the destination. As the data is transferred the commands contained in the data structure are performed and the data is modified as directed by the commands.

System and method for modifying data transferred from a source to a destination

A system and method for enabling a processor to access a memory not directly coupled to the processor. A memory request, including a request identifier field, is issued by a processor to a local memory management unit (MMU). Using the request identifier field, the local MMU determines whether the memory request should be issued by the local memory management unit (MMU) to a local memory, or should be transferred by the local MMU to a remote MMU and issued by the remote MMU to a remote memory, the remote memory associated with a different processor. In this manner, the remote MMU issues certain memory requests on behalf of the local processor and returns any results back to the local processor.

Full access to memory interfaces via remote request

A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a 'free' buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.

Hypertransport data path protocol

A buffer-management technique efficiently manages a set of data buffers accessible to first and second devices interconnected by a split transaction bus, such as a Hyper-Transport (HPT) bus. To that end, a buffer manager controls access to a set of 'free' buffer descriptors, each free buffer descriptor referencing a corresponding buffer in the set of data buffers. Advantageously, the buffer manager ensures that the first and second devices are allocated a sufficient number of free buffer descriptors for use in a HPT data path protocol in which the first and second devices have access to respective sets of free buffer descriptors. Because buffer management over the HPT bus is optimized by the buffer manager, the amount of processing bandwidth traditionally consumed managing descriptors can be reduced.

Buffer management technique for a hypertransport data path protocol

A method for identifying data is provided that includes receiving a data stream and performing a hashing operation on a portion of the data stream in order to identify a key that reflects an identity associated with the data stream. The method further includes storing a plurality of first and second hash table entries and comparing the key to the first and second hash table entries in order to evaluate if there is a match between the key and the first and second hash table entries.

System and method for identifying data using parallel hashing

A technique for enabling a processor to access a memory not directly coupled to the processor. According to the technique, a local processor accesses a remote memory by issuing a memory request that contains an indicator that indicates the request is addressed to the remote memory. The request is then transferred to a remote memory management unit (MMU) coupled to the remote memory. The remote MMU acts as a proxy and issues the memory request to the remote memory on behalf of the local processor. The results of the request, if any, are returned to the local processor.

A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.

Packet striping across a parallel header processor

A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

Sequence control mechanism for enabling out of order context processing

A technique is provided for use in testing replicated components (e.g., identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test inputs may be broadcast, in parallel, from a single test interface to each of the replicated components of the electronic device under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the electronic device, that compares the respective test outputs to each other and generates a fault signal if corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface, and its assertion may indicate that one or more of the replicated components may be defective. The respective test outputs may be multiplexed to permit output via an external interface of respective test outputs from a selected component. These respective test outputs may be compared to expected values therefor whereby to determine presence and/or nature of defects in the replicated components.

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Cary, NC, United States of America

Jeffery B Scott