Intel Corporation

Jefferson Amstutz

Gabor Liktor

Travis T Schluessler

Ingo Wald

Atsuo Kuwahara

Carson Brownlee

Johannes Guenther

Michael Doyle

Carsten Benthin

Abhishek R Appu

Joydeep Ray

Elmoustapha Ould-Ahmed-Vall

Karthik Vaidyanathan

Ankur N Shah

Jacek Kwiatkowski

Altug Koker

Nikos Kaburlasos

Kai Xiao

John H Feit

Deepak Shashidhar Vembar

Sayan Lahiri

Vivek Tiwari

Balaji Vembu

Kamal Sinha

James M Holland

Josh B Mastronarde

Pattabhiraman K

Radhakrishnan Venkataraman

Attila Afra

Attila Tamas Afra

An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array

Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.

Apparatus and method for efficient distributed denoising of a graphics frame

An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

Apparatus and method for hierarchical beam tracing and packet compression in a ray tracing system

Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.

Thread serialization, distributed parallel programming, and runtime extensions of parallel computing platform

An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.

Adjusting graphics rendering based on facial expression

Growing community of inventors

Austin, TX, United States of America

Jefferson Amstutz