Intel Corporation

Jeff Wight

Nasser A Kurd

David J O'Brien

Chakrapani Pathikonda

R Tim Frodsham

Mike J Tripp

Anne Meixner

Sarah E Bates

Rajay R Pai

In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.

Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Pad cells for a 2/N mode clocking scheme

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Beaverton, OR, United States of America

Jeff Wight