Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Jeff W Wolford

Robert A Lester

Walter G Fry

Jeffrey C Stevens

Todd J Deschepper

Russ Wunderlich

Robert L Woods

Jeffrey T Wilson

Richard J Tomaszewski

Shaun V Wandler

Danny Higby

Michael F Angelo

Paul R Culley

Arnold Thomas Schnell

Peter K Lee

Phillip M Jones

Charles J Stancil

Robert C Elliott

Randall L Hess

David R Wooten

Michael P Moriarty

Roger E Tipley

Maria L Melo

John A Landry

Christopher C Wanner

Michael S Bunker

Leonard E Russo

Walter A Gaspard

David E Murray

Jeff Stevens

William M Vaughn

Techniques for indicators for storage cells are provided. In one aspect, an indicator is provided that indicates if a portion of storage cells of a storage device contains a pre-defined value. In another aspect, a range of storage cells are initialized to a known value. An indicator may be set to indicate the range of storage cells has been initialized to the known value. In yet another aspect, a request for the indicator may be sent to a storage device. Based on the indicator, initialization of the storage device may be bypassed.

Indicators for storage cells

A method of enhancing security of a storage component communicating with a host processor over a bus comprises: receiving from the bus by the storage component one of a security unlock command, set password command, security disable command and security erase command along with a password associated therewith; determining a security state in which the storage component is operating at reception of the received command; determining if an enhanced security mode is enabled at reception of the received command; and performing security steps of the received command based the determined security state and the determined security mode.

Method of securing access to a hard disk drive of a computer system with an enhanced security mode

A system and method is disclosed for placing an electronic apparatus into a protected state in response to environmental data. The method discloses: receiving a set of environmental data applicable to an electronic apparatus; generating an environmental status applicable to the electronic apparatus based-on the environmental data; and placing the electronic apparatus into a protected state based-on the environmental status. The system discloses an environment characterization module which receives a set of environmental data applicable to an electronic apparatus, and generates an environmental status applicable to the electronic apparatus based-on the environmental data; and an apparatus protection module which places the electronic apparatus into a protected state based-on the environmental status.

System and method for placing an electronic apparatus into a protected state in response to environmental data

A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registers are programmed during boot-up of the computer system by assigning a subset of peripheral devices, bus agents, requesters, or bus masters to either a high priority ring or a low priority ring, if two levels of arbitration are used. The status of a low priority device can be elevated to equal priority with a high priority device by assigning the low priority device to a high priority port within the high priority ring if certain circumstances occur. Namely, if data transfers to or from the low priority device are terminated, then the low priority device will be promoted to a high priority device so that it need not wait until after the all high priority device requests have been polled. Instead, the elevated low priority device is placed on the same level of priority as the high priority devices so that its request can be readily serviced and the transaction completed during a data transfer retry operation.

Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus. The master interface then is responsible for understanding the protocol of the expansion bus and converting the IMAX master bus signals to signals compatible with the expansion bus. In addition, a dedicated target IMAX bus may also be provided for coupling internal targets within the South bridge to masters on the expansion bus through a common expansion target interface.

Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals. The IMAX target bus includes both an inbound bus and an outbound data bus for driving out data requested as part of a read cycle to an internal target device.

Computer system with bridge logic that includes an internal modular

An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

Direct memory access controller having programmable timing

A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion logic for passing to the host controller over the serial bus. The host controller includes circuitry for processing the data between the serial bus and a host bus. The host controller further includes 8042 emulation logic for providing a hardware compatible interface to the keyboard controller. The 8042 emulation logic also includes circuitry for communicating over the serial bus during times when the serial bus has not yet been initialized.

Universal serial bus keyboard system

A method and apparatus for providing secure and private keyboard communications in a computer system. A request for private keyboard communications causes the computer's processor to enter into system management mode by generating an system management interrupt. A secure system management interrupt handler then directs specialized hardware to intercept and divert keyboard interrupts, such that data entered via the keyboard is only communicated to a non-readable black box security device that controls access to protected system resources. Keyboard data is thereby protected from interception by malicious software.

Method and apparatus for providing secure and private keyboard

An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

First arbiter coupled to a first bus receiving requests from devices

A circuit for preventing a non-conforming PCI bus master from performing cycles where the address driven is not provided soon enough for receiving circuitry to latch the address. The circuit modifies the bus grant signal to force the non-conforming PCI bus master to temporarily release the bus instead of performing a second data transfer cycle within the same bus access so that a conforming cycle is subsequently performed when the bus is reacquired by the non-conforming PCI bus master. The circuit forces the non-conforming PCI bus master off the bus even though the non-conforming PCI bus requests the bus and an arbiter has granted the bus to the non-conforming PCI bus master.

Non-conforming PCI bus master timing compensation circuit

Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

System for awarding the highest priority to a microprocessor releasing a

A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

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Spring, TX, United States of America

Jeff W Wolford