Dell USA L P

Jeff Savage

Doron Gan

Alan E Brown

Rick Finch

Method and apparatus for detecting the presence of a semi-compliant PCI device in a secondary expansion slot of a PC and instructing the user to reinsert the device into one of the primary slots are disclosed. In one embodiment, upon detection of a semi-compliant PCI device in a secondary slot, a video image instructing the user to reinsert the device into one of the primary slots is displayed on a display of the PC. Operation remains suspended until the device is relocated to a primary slot. In a presently preferred embodiment, a hardware enhancement to a PCI-to-PCI bridge connecting a primary PCI bus to a secondary BCI bus enables the device to operate flawlessly on the secondary PCI bus, such that the user remains unaware of the otherwise undesirable situation.

Technique for supporting semi-compliant PCI devices behind a PCI-to-PCI

A last power state apparatus including a power supply controller having a battery-backed memory bit for retaining the power state of an electronic device during a failure of a primary power source. The battery is preferably a lithium type battery and the power supply preferably provides a flea power signal when primary power is available to maintain the state of the memory bit even if the power supply is off. The controller asserts a power status signal to the power supply based on the state of the memory bit, so that the power supply remains off or powers up as appropriate when primary power is next available. A momentary power switch is used to manually turn on and off the power supply and the electronic device by toggling the memory bit. The electronic device, which is typically a computer system, provides signals to the power supply controller to turn off the device. Further, the computer can enable an interrupt to prevent the user from turning off the device until after vital functions are completed. Also, other events, such as a real time clock (RTC) alarm, or the activation of a modem are monitored to toggle the memory bit to turn on the device. The RTC also monitors the battery voltage and provides a standard battery valid signal, where the controller resets the memory bit to a default off state if the battery voltage falls below a predetermined minimum value.

Power supply control apparatus using last power state memory

A method and apparatus for performing cache snoop testing on personal computers using software to initiate DMA cycles. The computer system includes an extended capabilities parallel port (ECP), which includes a 16 bit first-in first-out buffer (FIFO) that can be accessed in a test mode where software can manually write and read the FIFO. This FIFO in the ECP parallel port is used according to the present invention to implement cache snoop testing diagnostics on personal computers. In the preferred embodiment, various hardware subsystems such as system memory, the ECP port, and the DMA controller are tested first to ensure that, if a failure occurs during cache testing, the system can differentiate between cache snoop failures and other subsystem failures. Cache snoop testing according to the present invention uses the capability provided by the ECP parallel port to generate DMA cycles which transfer data from the ECP FIFO buffer into the system memory via software. Various algorithms can be used to perform cache snoop testing depending upon the cache architecture, i.e., write-through versus write-back and whether the cache system includes only first or both first and second level cache systems. Therefore, cache snoop testing can be performed reliably in software without the need for expensive custom test hardware.

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Austin, TX, United States of America

Jeff Savage