Lsi Logic Corporation

Lsi Corporation

Jeff S Brown

Mark Franklin Turner

Marek J Marasch

Jonathan W Byrn

Jay Daugherty

Miguel A Vilchis

Paul Dorweiler

Chang Ho Jung

Joseph E Simko

Jay D Harker

Carol A Anderson

Hiren R Patel

Gerald R Haag

John Gatt

A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.

System and method for decreasing signal integrity noise by using varying drive strengths based on likelihood of signals becoming victims

Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages.

Overshoot suppression for input/output buffers

One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.

Input/output core design and method of manufacture therefor

Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.

Architecturally independent noise sensitivity analysis of integrated circuits having a memory storage device and a noise sensitivity analyzer

A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.

Sequential element low power scan implementation

A modulated clock, a method of providing a modulated clock signal, an integrated circuit including a modulated clock and a library of cells including a modulated clock. In one embodiment, the modulated clock includes (1) a clock controller configured to generate a digital control stream and (2) clock logic circuitry having a first input configured to receive a clock signal and a second input configured to receive the digital control stream. The clock logic circuitry is configured to provide a modulated clock signal in response to the clock signal and the digital control stream, wherein the modulated clock signal has an effective frequency that differs from the first frequency.

Modulated clock, an IC including the modulated clock and a method of providing a modulated clock signal for power control

A D flip-flop (DFF), a method of operating a DFF, a latch and a library of standard logic elements including standard logic elements corresponding to a DFF and a latch. In one embodiment, the DFF has a data input and a data output and includes: (1) a master stage passgate coupled to the data input, (2) a master stage coupled to the master stage passgate and having a hysteresis inverter with feedback transistors of opposite conductivity, (3) a slave stage passgate coupled to the master stage and (4) a slave stage coupled between the slave stage passgate and the data output and having a hysteresis inverter with feedback transistors of opposite conductivity.

D flip-flop having enhanced immunity to single-event upsets and method of operation thereof

A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.

Method of generating a restricted inline resistive fault pattern and a test pattern generator

A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.

Latch and DFF design with improved soft error rate and a method of operating a DFF

A method and apparatus is provided for replacing defective storage cells within a memory device having twisted bit lines. If a defective storage cell is discovered, the row containing that storage cell can be re-mapped to the neighboring row or the memory array. Each successive neighboring row is also re-mapped to succeeding neighboring rows by incrementing or decrementing the row addresses. This will cause the addresses to essentially shift one address value toward the redundant set of rows, and one redundant row will be subsumed for every defective row within the array. Whenever an address is shifted across a twist region, the data of that address is purposely inverted in binary voltage value (i.e., converted from a binary 1 to a binary 0, and vice versa) to accommodate the twisting of the true and complementary bit line locations.

Method and apparatus for replacing a defective cell within a memory device having twisted bit lines

An on-chip apparatus and method for measuring signal skew between two on-chip signals are provided. The apparatus and method generate a pulse train which is at a first state during a time period between a clocking of a circuit component and a time at which the circuit component generates an output signal, and a second state between clockings of the circuit component. The pulse width of the pulses in the pulse train is representative of the skew, i.e. change of phases or timing, in the signal due to the presence of the component. The pulse train may further be pseudo-clock divided to generate more measurable pulses. The output from is produced using a single output pad. The apparatus and method produce a long measurable pulse width on a single output pad. A pulse width of 10 s of ns is achievable instead of 1-2 ns as in the known art. The pulse width measurement is done with a single tester channel instead of two as in the known art.

Apparatus and method for signal skew characterization utilizing clock division

A method and apparatus for accommodating irregular memory write word widths allow for writing to multiple rows in a memory so as to reduce or eliminate holes in the address read space. First and second memory blocks are provided that include a first bitcell selectable by a first write bitline and a second bitcell selectable by a second write bitline. Where a write word width is not equal to a read word width and is not some factor of a power of two times the read word width, the column decode to read out the entire word is not a power of two, and holes in the read address space will exist. When the write address is even, a first range of bits is written to the first block on a first write bitline, a second range of bits is written to the second block on the first write bitline, and a third range of bits is written to the first block on a second write bitline. When the write address is odd, a first range of bits is written to the second block on the first write bitline, a second range of bits is written to the first block on the first write bitline, and a third range of bits is written to the second block on the second write bitline. Reading of data from the memory occurs as with a typical memory structure.

Method and apparatus for accommodating irregular memory write word widths

A mechanism is provided for self timing a memory circuit to compensate for sense amplifier imbalance. The self timing mechanism comprises two self timed sense amplifiers. A first self timed sense amplifier reads a first state and a second self timed sense amplifier reads a second state. The control logic deactivates the real sense amplifiers in response to the slower of the two self timed sense amplifiers. Thus, even if there is a layout or processing variance, which causes the sense amplifiers to have a non-zero offset voltage and favor a certain output state when the inputs are equal, the real sense amplifiers are able to read the states of the memory cell.

Sense amplifier imbalance compensation for memory self-timed circuits

A sense amplifier includes a voltage supply terminal, first and second differential bit line inputs and a differential amplifier. The differential amplifier has first and second amplifier inputs, which are coupled to the first and second differential bit line inputs, respectively, and has an amplifier output. A first transistor is coupled between the voltage supply terminal and the first bit line input and has a current control terminal coupled to the second bit line input. A second transistor is coupled between the voltage supply terminal and the second bit line input and has a current control terminal coupled to the first bit line input.

Differential sense amplifier with voltage margin enhancement

A circuit in a memory device and a method for precharging at least one bit line in the memory device. The circuit includes a primary precharger and a secondary precharger in communication with the bit line. The secondary precharger gradually precharges the bit line before the primary precharger precharges the bit line between memory operations.

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Fort Collins, CO, United States of America

Jeff S Brown