Avago Technologies General IP (singapore) Pte. Ltd.

Cortina Systems Corporation

Avago Technologies General IP Pte, Ltd.

Jeff P Kirsten

Stephane Dallaire

Shawn Lawrence Scouten

Malcolm Stevens

Kevin Parker

A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.

Integrated jitter compliant low bandwidth phase locked loops

A testing apparatus includes one or more trace banks. Each trace bank includes (1) an input switch operable to couple an input port to one of multiple output ports, (2) an output switch operable to couple one of multiple input ports to one output port, and (3) transmission lines of different lengths coupled between the output ports of the input switch and the input ports of the output switch. The trace banks can be cascaded using cables to connect their output and input ports. The input and output switches in the trace banks are controlled to provide a transmission path of the desired length.

Switched length match transmission path instrument

Switched length matched transmission path instrument

Growing community of inventors

Folsom, CA, United States of America

Jeff P Kirsten