National Semiconductor Corporation

Matsushita Electric Industrial Co., Ltd.

Fairchild Semiconductor Corporation

Jeff M Huard

Craig M Davis

Yukihiro Yagi

Masayuki Nakaimuki

Shinichi Takahashi

Robert J Bosnyak

A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals for the feedback signal are: increased when small fractional divisors (&lt;1/2) causing a lagging phase relationship or large fractional divisors (&gt;1/2) causing a leading phase relationship are sensed; and decreased when small fractional divisors (&lt;1/2) causing a leading phase relationship or large fractional divisors (&gt;1/2) causing a lagging phase relationship are sensed.

Fractional-N phase-lock loop with delay line loop having

A closed-caption decoder which uses separate clock generators to produce the sampling frequencies for the clock run-in signal and the data portion of the closed-caption signal. Each of the clock generators generates its signal from a common 12 MHz reference clock signal. The timing of the sampling clock signal for the closed-caption data is advanced at the start of the sampling interval to reduce the total timing errors in the sampling of the closed-caption data. Additionally, the decoder can adaptively select one of four edges of the clock run-in signal to use as its synchronizing reference. Furthermore, the decoder may be adapted to recognize more than one start byte pattern.

Closed-caption decoder circuit having robust synchronization features

A multi-port memory cell utilizes a storage cell to define complementary data storage nodes. Each read port of the memory cell includes two FETs respectively coupled between one of a pair of complementary data-out lines and a read enable line to isolate the read ports. Each of the gates of the two read port FETs is connected to one of the corresponding data storage nodes. The storage cell is read by pulling current from the read enable line and monitoring the difference between the complementary data-out lines.

High speed, multi-port memory cell utilizable in a BICMOS memory array

An input protection structure effectively protects input circuitry from positive-going ESD pulses. The input protection structure includes a transistor having a reduced beta, connected in series with one or more diodes between the input pin and VCC. In one embodiment, the transistor having reduced beta is constructed in the same manner as a fuse device. The structure is formed in an integrated fashion, without the need for metallic interconnections within the structure itself, thereby decreasing impedance while minimizing surface area in the integrated surface.

ESD low resistance input structure

A circuit which provides additional drive current during substantially the entire transition of an output signal from a logical one to a logical zero state, thereby causing the pulldown transistor in the TTL output stage to rapidly turn on, providing increased switching speed between logical one and logical zero output state for a given power consumption. Alternatively, for a given switching speed, power consumption is reduced.

Growing community of inventors

Puyallup, WA, United States of America

Jeff M Huard