Hewlett-Packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Jeff M Carlson

William C Galloway

Ryan A Callison

Mark J Thompson

Thomas W Grieff

Albert H Chang

Christopher Garza

A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.

Memory controller interface with XOR operations on memory read to accelerate RAID operations

Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amount of free space available in the write buffer. When the data in the write buffer approaches the capacity of the write buffer, the system prepares for a potential disconnect of the write initiating device from the bridge device. Data alignment with cache line boundaries is maintained upon disconnect by adjusting the available free space in the write buffer to equal a multiple of a cache line amount of data. The write initiating device is disconnected when the data in the write buffer equals a write buffer full status.

Disconnecting a device on a cache line boundary in response to a write command

Efficient memory operation is provided by maintaining alignment with cache line boundaries in response to a read command. A prefetching scheme is used to limit the amount of operations needed to respond to a read command. In addition, the prefetch amount is initially adjusted where the starting address of the read request falls in between cache line boundaries. The adjusted read amount is determined based on the misaligned portion from the starting address of the read request to the nearest cache line boundary outside of the requested data block, such that the adjusted read amount ends on a cache line boundary. Subsequent read requests to the same data block will thereby begin at the last cache line boundary and end upon a subsequent cache line boundary by providing the pre-configured prefetch data amount corresponding to the requesting master device. Efficient bus utilization and memory controller operation efficiency is maximized by allowing the memory control to operate and respond to read requests in data amounts maintaining cache line alignment.

Providing data in response to a read command that maintains cache line alignment

A FIFO with locked exchange capability is disclosed. The FIFO has a memory for storing and retrieving data submissions, a write address generator and a read address generator for sequentially addressing the memory. A difference counter maintains the difference between the number of writes to the queue and reads from the queue. The net difference, as tracked by the counter is a measure of the FIFO utilization. To detect the queue full condition, a comparator compares the maximum FIFO stack depth against the counter output. The result of this comparison is latched and provided to a write strobe generator so that, in a subsequent write operation, if the FIFO is full, the write strobe from the producer is blocked and the data will not be written to the FIFO. Otherwise, the write strobe from the producer is passed to the memory. Additionally, a remaining space count is maintained in a status register. During operation, a bus master performing the read-modify-write cycle to the FIFO reads the status register to find the available space in the FIFO and immediately writes the data to the FIFO. If the read returns a zero, indicating that the FIFO is full, the bus master requeues the data for another read- modify-write cycle as it knows that the data has not been stored in the FIFO.

Locked exchange FIFO

A bridge circuit for holding off primary interrupts signaling the completion of a block data transfer from a second bus to a system bus until the data has cleared the bridge circuit. The bridge circuit includes an interrupt control circuit for receiving up to seven primary interrupt signals corresponding to seven sets of bus grant-request lines on a second bus. Each bus grant-request set is assigned a data FIFO for synchronizing the transfer of data from the second bus to a system bus. The interrupt control circuit provides an interrupt to the system bus which corresponds to the primary interrupt only after the associated data FIFO is empty, thereby preventing data coherency problems in system memory.

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Cypress, TX, United States of America

Jeff M Carlson