Intel Corporation

Jeff L Rabe

David J Harriman

David I Poisner

Zohar Bogin

Brian K Langendorf

Stephen Anthony Fischer

Bruce A Young

Gary A Solomon

Darren L Abramson

Puthiya K Nizar

Vincent E VonBokern

David J McDonnell

Michael G LaTondre

Tom A Sutera

According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.

Power management method for a computer system having a hub interface architecture

A method for controlling device temperature. The method involves determining access rate to a component, comparing the access rate with a predetermined threshold modified by a weighted value and controlling the temperature of the component through corrective action.

Method and apparatus to control device temperature

A bus bridge which intercepts synchronization events and selectively flushes data in buffers within the bridge is disclosed. The bridge insures data consistency by actively intercepting synchronization events, including, interrupts, processor accesses of a control status registers, and I/O master accesses of shared memory space. Interrupt signals may be routed through the bridge, which includes a bridge control unit comprised of state machine logic for managing data transfers through the bridge. In response to an interrupt signal from an agent on a bus, the bridge control unit flushes posted data before allowing a processor to process the interrupt signal. The bridge control unit further requires that the bridge complete all posted writes generated from a first bus before the bridge accepts a read generated from a second bus. The bridge control unit additionally insures strict ordering of accesses through the bridge. Data consistency is thereby realized without requiring the bridge to participate in the cache coherency protocol of the primary bus.

Bridge buffer management by bridge interception of synchronization events

A collection buffering scheme for a computer system having agents of a pre-emptible bus and a non-pre-emptible bus. An agent of the non-pre-emptible bus, having a data width capability of N bits, when receiving a grant to write to the pre-emptible bus, writes instead to a collection buffer capable of holding a block of more than one N bit data segments. When the collection buffer is filled, the collection buffer writes the entire block of data segments over the pre-emptible bus to a CPU or memory of the computer system. Preferably, the collection buffer is filled when the block size is equal to the data width capability of the pre-emptible bus, such that a single write to the pre-emptible bus utilizes the entire capacity of pre-emptible in a given data transaction. Further, where the system has a CPU posting buffer, a system lock-up prevention negotiator is provided that drains and disables the CPU posting buffer during the data transaction.

Collect all transfers buffering mechanism utilizing passive release for

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Gold River, CA, United States of America

Jeff L Rabe