Intel Corporation

Jeff J Baxter

Nazar A Zaidi

James R Anderson

Ernest T Lampe

Hong Wang

Konrad K Lai

Gary N Hammond

Ralph Michael Kling

Ken Shoemaker

Anand B Pai

Mike J Morrison

In general, the PBVT structure provides an effective method of filtering a stream of hardware generated prefetches by eliminating prefetch addresses that have proven to be inaccurate in the past. When compared to a design that uses a PFB of equal number of entries, the PBVT along with a small PFB provides virtually equivalent prefetch accuracy and miss rate reduction while using much less hardware area (97% less data storage space for a 1024-entry PFB case).

Method and apparatus for filtering prefetches to provide high prefetch accuracy using less hardware

An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.

Method and apparatus for access demarcation

In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. The dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. As each instruction is dispatched for execution from the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution. In this manner, an out-of-order processing scheme is implemented that efficiently accounts for data dependency between processed instructions.

Dependency matrix

A system for accelerating instruction restart in a microprocessor. An instruction is fetched. The instruction is placed in a macro-instruction queue and sent to the decoder. The instruction is decoded in order to produce at least one micro-operation. The micro-operation is executed, and the microprocessor checks for instruction restart conditions. If an instruction restart condition is found, the instruction restart function is performed. The instruction restart function includes decoding the instruction stored in the macro-instruction queue and executing the corresponding micro-operations.

Method and apparatus for accelerated instruction restart in a

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Los Gatos, CA, United States of America

Jeff J Baxter