Jeff Evertt

Jahanshir J Javanifard

Rodney R Rozman

Joseph W Tsang

Jerry A Kreifels

Jeffrey J Peterson

Christopher John Haid

Vishram Prakash Dalvi

A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

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Kirkland, WA, United States of America

Jeff Evertt