Agere Systems Inc.

Noble Device Technologies Corporation

Jeff Devin Bude

Kwok K Ng

Peide Ye

Bin Yang

Isik C Kizilyalli

Clifford Alan King

Malcolm Carroll

Kent Smith

A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

III-V power field effect transistors

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

Semiconductor devices with reduced active region defects and unique contacting schemes

An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A drift region of the second conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the source and drain regions, the drift region having an impurity doping concentration greater than about 2.012 atoms/cm. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer. The device further includes a gate formed on the insulating layer at least partially between the source and drain regions, and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region. A substantially vertical distance between the buried layer and the drift region, and/or one or more physical dimensions of the buried layer are configured so as to optimize a power density of the device relative to at least one of an on-resistance and a maximum drain current of the device.

Semiconductor device having improved power density

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Danville, CA, United States of America

Jeff Devin Bude