Intel Corporation

Jeff C Morriss

Debendra Das Sharma

Zuoguo Wu

Mohiuddin M Mazumder

Ajay V Bhatt

Sudarshan Bala Cadambi

Shaun Knoll

Mahesh U Wagh

Venkatraman Iyer

Puthiya K Nizar

Richard M Haslam

David J Harriman

Kemal Aygun

Zhiguo Qian

Andrew M Volk

Sanka Ganesan

Richard J Dischler

Yidnekachew S Mekonnen

Timothy D Wig

Narasimha R Lanka

Jong-Ru Guo

Eduard Roytman

Shelagh Ann Callahan

Anupriya Sriramulu

Telesphor Kamgaing

Georgios C Dogiamis

Henning Braunisch

Shreekant S Thakkar

Robert J Greiner

Mathew J Manusharow

Wilfred Gomes

Ram S Viswanath

Rajasekaran Swaminathan

Sriram Srinivasan

Hyung-Jin Lee

Gregorio R Murtagian

Yu Zhang

Peter J Ruscito

Yu Amos Zhang

Ajay Balankutty

Pranav H Mehta

Said Rami

Narayanan S Iyer

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Extending multichip package link off package

A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

High performance interconnect

Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

Single side band transmission over a waveguide

Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

Rlink&#x2014;die to die channel interconnect configurations to improve signaling

A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical 'signal' interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

Rlink-ground shielding attachment structures and shadow voiding for data signal contacts of package devices; vertical ground shielding structures and shield fencing of vertical data signal interconnects of package devices; and ground shielding for electro optical module connector data signal contacts and contact pins of package devices

In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Providing a serial protocol for a bidirectional serial interconnect

In one embodiment, the present invention includes an apparatus having a random number generator to generate a random number responsive to a first command from a host controller and a logic to generate a device identifier for the apparatus. The apparatus can provide a reply to the host controller including the random number responsive to an identification request from the host controller corresponding to the device identifier. Other embodiments are described and claimed.

Assigning addresses to devices on an interconnect

In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a data packet for communication along an interconnect and to transmit the data packet. This data packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

A skew correction circuit includes a first circuit and a second circuit. The first circuit generates at least one pulse train signal in response to a data bit signal and a first strobe signal. A duty cycle of the pulse train signal is indicative of a degree of skew between the data bit signal and the strobe signal. The second circuit is coupled to the first circuit to produce a second strobe signal and regulate a timing relationship between the data bit signal and the second strobe signal based on the duty cycle of the pulse train.

Skew correction circuit

A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

Method and system for implementing control signals on a low pin count bus

Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

M&A for exchanging date, status and commands over an hierarchical serial

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Los Gatos, CA, United States of America

Jeff C Morriss