Fei Comapny

Lsi Logic Corporation

Jeff Blackwood

Stacey Stone

Michael Schmidt

Brennan Peterson

Craig Henry

Guus Das

Jason Harrison Arjavac

Tom Miller

Michael Moriarty

Cliff Bugge

Valerie Brogden

Matthew Bray

Dhruti Trivedi

Todd Templeton

Paul Keady

Larry Dworkin

Jr Brian Routh

A method for TEM sample preparation and analysis that can be used in a FIB-SEM system without re-welds, unloads, user handling of the lamella, or a motorized flip stage. The method allows a dual beam FIB-SEM system with a typical tilt stage to be used to extract a sample to from a substrate, mount the sample onto a TEM sample holder capable of tilting, thin the sample using FIB milling, and rotate the sample so that the sample face is perpendicular to an electron column for STEM imaging.

High throughput TEM preparation processes and hardware for backside thinning of cross-sectional view lamella

A protective layer is applied to a work piece to protect the surface during charged particle beam processing by directing a fluid toward the surface. The surface is preferably not touched by the applicator. Ink jet print-type print heads are suitable applicators. Ink jet-type print heads allow a wide variety of fluids to be used to form the protective layer. Useful fluids that form protective layers include colloidal silica having small silver particles and hydrocarbon-based inks.

Protective layer for charged particle beam processing

A method and apparatus for preparing thin TEM samples in a manner that reduces or prevents bending and curtaining is realized. Embodiments of the present invention deposit material onto the face of a TEM sample during the process of preparing the sample. In some embodiments, the material can be deposited on a sample face that has already been thinned before the opposite face is thinned, which can serve to reinforce the structural integrity of the sample and refill areas that have been over-thinned due to a curtaining phenomena. In other embodiments, material can also be deposited onto the face being milled, which can serve to reduce or eliminate curtaining on the sample face.

Methods for preparing thin samples for TEM imaging

An improved method and apparatus for S/TEM sample preparation and analysis. Preferred embodiments of the present invention provide improved methods for TEM sample creation, especially for small geometry (&#x3c;100 nm thick) TEM lamellae. A novel sample structure and a novel use of a milling pattern allow the creation of S/TEM samples as thin as 50 nm without significant bowing or warping. Preferred embodiments of the present invention provide methods to partially or fully automate TEM sample creation, to make the process of creating and analyzing TEM samples less labor intensive, and to increase throughput and reproducibility of TEM analysis.

Method for creating S/TEM sample and sample structure

Method for creating S/tem sample and sample structure

A coating is applied to a work piece in a charged particle beam system without directing the beam to work piece. The coating is applied by sputtering, either within the charged particle beam vacuum chamber or outside the charged particle beam vacuum chamber. In one embodiment, the sputtering is performed by directing the charged particle beam to a sputter material source, such as a needle from a gas injection system. Material is sputtered from the sputter material source onto the work piece to form, for example, a protective or conductive coating, without requiring the beam to be directed to the work piece, thereby reducing or eliminating damage to the work piece.

Sputtering coating of protective layer for charged particle beam processing

A silicon device which includes a silicon substrate and a bond pad array on the silicon substrate which is configured to be conductively connected to bond wire. The bond pad array consists of a plurality of bond pads which are vertically staggered on the silicon substrate. The vertical staggering allows the bond pads to be packed closer together on the silicon substrate, thereby reducing the horizontal space which is consumed by the bond pads on the silicon substrate, and thereby resulting in a reduction in die size. Preferably, the bond pads are also horizontally staggered on the silicon substrate, thereby allowing the bond pads to be spaced even closer together.

Vertically staggered bondpad array

An integrated circuit test apparatus and a method for testing an integrated circuit are described. The integrated circuit test apparatus includes a holder adapted to receive a wafer, where a frontside of the wafer is accessible to be probe tested by electrically conducting probe needles during which a backside of the wafer is accessible to be scanned by an optical scanning mechanism. The scanning mechanism can optically detect photoemission-generated defects resulting from electrical stimuli applied to the integrated circuits via the probe needles. The holder is coupled to a three-dimensional translational mechanism that will allow for automated multi-die test probing.

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Portland, OR, United States of America

Jeff Blackwood