Texas Instruments Corporation

Other

Jeff A West

Thomas Dyer Bonifield

Jiong-Ping Lu

Byron Lovell Williams

Ricky A Jackson

Francis Gabriel Celii

Robert Kraft

Guoqiang Xing

Honglin Guo

Margaret Simmons-Matthews

Andrew McKerrow

Kenneth Joseph Newton

Rajesh Tiwari

James L Oborny

Daniel Joseph Stillman

Zhicheng Tang

David Permana

Scott Alexander Johannesmeyer

Norman Armendariz

William John Antheunisse

Ramyanshu Datta

Andrew Ralston

Albert Cheng

Brock W Fairchild

Chris M Bowles

Tim A Taylor

The present invention relates to a punch down tool comprising a handle, a holder extending from the handle, and a down blade assembly operably connected to the holder. The down blade assembly comprises at least two down blades, wherein the down blades include a U-shaped cut out configured thereon for accommodating a wire that is to be crimped into a connector. The tool further comprises a housing in which the down blades are disposed such that the down blades are linearly displaceable within the housing. A cutting blade is also provided on the housing.

Punch down tool

It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.

Reliability improvement of polymer-based capacitors by moisture barrier

A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate

A dual damascene process flow for forming interconnect lines and vias in which at least part of the via () is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD () and IMD (). After the at least partial via etch, a BARC () is deposited over the structure including in the via (). Then, the trench () is patterned and etched. Although at least some of the BARC () material is removed during the trench etch, the bottom of the via () is protected.

Process flow for dual damescene interconnect structures

A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Method of preventing seam defects in isolated lines

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Dallas, TX, United States of America

Jeff A West