National Semiconductor Corporation

Cree Microwave, Inc.

Jeff A Babcock

Yuri Mirgorodski

Saurabh Desai

Natalia Lavrovskaya

John Mason

Johan Agus Darmawan

Jamal Ramdani

Natasha Lavrovskaya

Steve Adler

Todd Thiebeault

Natasha Layrovskava

Ly Diep

Saurahh Desai

A method is provided for enhancing charge storage in an EPROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.

[object Object]

In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a control gate and a third poly strip coupled to a read transistor gate.

Non-volatile memory cell with fully isolated substrate as charge storage

A heating element is utilized to improve the bias conditions of an EPROM cell during program and erase operations. The heating element can also be used to anneal or condition the cell for improved charge storage. During a program or an erase operation, the cell's control gate and read transistor are set to ground. The heating element then has a voltage potential applied across its terminals, causing current to flow in this resistor. As the current density increases, the resistor begins to generate heat. This heat is thermally coupled into the cell's floating gate, causing its temperature to rise.

In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a read gate and a poly-filled trench defining a control gate.

Non-volatile memory cell with poly filled trench as control gate and fully isolated substrate as charge storage

A bipolar transistor device architecture and method of manufacture uses doped glass on the sidewall of the emitter window opening to reduce the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. The doped glass sidewall also improves dopant loss in the oxide in the case in which an in-situ doped poly emitter is used. By using a doped sidewall glass, the sensitivity of dopant absorption that can potentially occur in un-doped spacers is removed. The proposed technique also provides a simple method for achieving narrow emitter window openings while simultaneously improving doping uniformity compared to implanted poly techniques. The technique also allows a self-aligned base to be performed, thereby allowing tighter spacing between the extrinsic base and the intrinsic base.

Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure

A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.

LDMOS transistor with improved gate shield

Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.

Growing community of inventors

Sunnyvale, CA, United States of America

Jeff A Babcock