Shaoxing Yuanfang Semiconductor Co., Ltd.

Jeevabharathi G

Ankit Seedher

Srinath Sridharan

Raja Prabhu J

Purva Choudhary

Rakesh Kumar Gupta

Sandeep Sasi

Shivam Agrawal

Akash Gupta

Nitesh Naidu

Bhupendra Sharma

Debasish Behera

Chandrashekar Bg

Nandini Ganig Bs

An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.

Inter-PLL communication in a multi-PLL environment

Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

Fast switching of output frequency of a phase locked loop (PLL)

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Bengaluru, India

Jeevabharathi G