Intel Corporation

Jeen Miin

Nhon Toai Quach

Sunny C Huang

Dean A Mulla

John Wai Fu

Nazar A Zaidi

Michael Paul Corwin

Stuart E Sailer

Huang Kuang Hu

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

Combined tag and data ECC for enhanced soft error recovery from cache tag errors

A method and an apparatus for error detecting and error recovering in a processor are described. In one embodiment, a system includes at least one cache, one execution unit, and an error detecting and recovering device. The error detecting and recovering device monitors information transferred between the processor components, such as a cache and an execution unit. Once an error is identified, the error detecting and recovering device suspends processor execution. After the error is recovered, the processor execution is resumed.

Using hardware or firmware for cache tag and data ECC soft error correction

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

A queuing system that avoids live-locking is provided. A representative implementation of this system 1) selects a first queue item pointed to by a rotating pointer if the first queue item is ready to be serviced, 2) selects a second queue item pointed to by a find-first-pointer if the first queue item is not ready to be serviced, and 3) updates the rotating pointer so that the rotating pointer points to a third queue item.

Method and apparatus for live-lock prevention

A system for processing caches misses includes a request miss buffer, secondary miss logic, and a request identifier buffer. When a request misses in a cache, information characterizing the request is provided to the request miss buffer and the secondary miss logic. The secondary miss logic determines whether the request may be merged with a pending bus transaction, and provides the request identifier buffer with a pointer to the request information. The pointer is stored at an entry associated with the pending bus transaction. For a load request, data returned by the bus transaction is routed to a targeted register, using the request information in the request miss buffer.

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Fremont, CA, United States of America

Jeen Miin