Hynix Semiconductor Inc.

Skhynix Inc.

Jee-Yul Kim

Beom-Ju Shin

Jong-Min Lee

Hi-Hyun Han

Chang-Ho Do

Yoon-Jae Shin

A memory system may include: a memory device storing data and including a memory interface in communication with a memory controller; and the memory controller controlling the memory device and including a controller interface in communication with the memory device, and, wherein, when the memory device is inaccessible, the memory controller requests a current state information including current operation mode of the memory interface from the memory device, and changes an operation mode of the controller interface to match the current operation mode of the memory interface according to the current state information received from the memory device.

Memory device, memory controller and memory system including them, and method for operating them for matching operation mode of memory interfaces

A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a program verify operation to program data to the memory blocks, and a controller configured to detect program error bit information as a result of the program verify operation, select a victim memory block among the memory blocks based on the detected program error bit information, and copy programmed data of the victim memory block.

Memory system and operating method for the same

A memory system may include: a memory device including a plurality of pages in which data are stored and a plurality of memory blocks which include the pages; and a controller suitable for storing data segments of user data corresponding to a write command received from a host, in the pages included in the memory blocks, generating map segments of map data corresponding to storage of the data segments and lists, and searching and updating the map segments through the lists.

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory blocks each block including a plurality of pages; and a controller including a memory, and suitable for buffering segments of user data and metadata for a command operation into the memory, and storing the buffered segments into a super memory block including two or more of the plurality of memory blocks during the command operation in response to a command, wherein, when the total size of to-be-stored data among the buffered segments of the memory is smaller than an unit size of the one shot program, the controller stores dummy data as well as the to-be-stored data into the super memory block.

Memory system and operating method of memory system

A memory system includes: a memory device including a plurality of pages which include a plurality of memory cells coupled to a plurality of word lines and in which data are stored, and a plurality of memory blocks in which the pages are included; and a controller including a memory, and suitable for storing data segments of user data corresponding to a write command received from a host, in pages included in a first memory block and a second memory block among the memory blocks and generating map data corresponding to storage of the data segments by sorting map segments of the map data according to logical informations of the data segments.

Memory system and method for mapping nonvolatile memories

A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage.

Trimming circuit of semiconductor memory apparatus and trimming method thereof

An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode.

Circuit for testing internal voltage of semiconductor memory apparatus

A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay time corresponding to a delay time of the DLL to output a delayed internal command signal; and an output enable signal generator for generating an output enable signal based on the delayed internal command signal and the DLL clock signal.

Semiconductor memory device including delay locked loop and method for driving the same

Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent upon a temperature variation, a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal, and a self refresh signal generating unit for receiving a self refresh entry signal and generating a self refresh signal of temperature compensated cycle under the control of the comparison result signal.

Memory device with self refresh cycle control function

An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address.

Semiconductor memory device

A semiconductor memory device is capable of reducing the current dissipation in a termination circuit and allowing a voltage level of a GIO line to rapidly reach a voltage level of a termination voltage when a termination operation is performed. The semiconductor memory device includes a global input/output line configured to transport data between a core region and an interface region, a main driving block configure to drive a voltage level of the global input/output line to predetermined termination voltage level in response to a termination enabling signal, and an auxiliary driving block configured to drive the is voltage level of the global input/output line to the predetermined termination voltage level in response to an over-driving signal, wherein the over-driving signal is enabled for a predetermined period of time during an initial period of an enabling interval for the termination enabling signal.

Semiconductor memory device and driving method thereof

A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals.

Semiconductor memory device having wafer burn-in test mode

A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.

Multi-wordline test control circuit and controlling method thereof

A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock; an output control unit for generating a select signal based on a column address strobe (CAS) latency signal and a delay time corresponding to a total delay time of the DLL being in a delay locked state; and an output enable signal generating unit for generating a plurality of output enable signals in response to the DLL clock and outputting a final output enable signal in response to the select signal.

Semiconductor memory device and method for driving the same

An internal address generator for use in a semiconductor memory device includes an address detector, a drive pulse generator, and a delay unit. The address detector generates a comparison signal by comparing a first address currently input with a second address previously input. The drive pulse generator generates a drive pulse in response to the comparison signal. The delay unit outputs the first address as the second address and delays the second address to thereby generate an internal address synchronized with the drive pulse in case that the first address is different from the second address.

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Kyoungki-do, South Korea

Jee-Yul Kim