Samsung Electronics Co., Ltd.

Jee-Kyoung Park

Hyung-han Lee

Yong-seok Shin

Seung-hwe Hwang

A computer having multi booting function with more than two boot-ROMs is disclosed. The boot-ROMs comprise a flash RAM, and have the same address space in the computer system. Preferably, the first boot-ROM is provided with a general boot program, and the second boot-ROM with detailed diagnostic program. Alternatively, the first boot-ROM is provided with a conventional boot program, and the second boot-ROM with reprogrammed or updated boot programs. Provided is a select signal generator for producing select signals which designate one of said boot-ROMs and a boot-ROM select circuit for producing control signals that selectively activate one boot-ROM in response to the memory control signals fed from the CPU and one of said select signals. The select signal generator includes a first and second reset switches for producing a first and second chip select signals, each designating the first and second boot-ROMs. Also, those first chip select signal and second chip select signal can be produced in response to an input of a specific key combination from the keyboard and keyboard controller.

Computer with multi booting function

A system for automatic fault detection and recovery in a computer system includes: a system fault detector, a halt time duration counter, and program and hardware recovery signal generators. The system fault detector is connected to a plurality of bus signal lines of a computer system to produce an output signal in response to an existence of an operating signal in the system bus. The halt time counter is operated in response to the output signal of the fault detector and clock signals to produce a set of count values each representing the passage of a predetermined time duration after a vanishing of the output signal of the fault detector. The program recovery signal generator produces a system management interrupt (SMI) signal when seven minutes have elapsed from the detection of the system halt. Also, the hardware recovery signal generator produces a reset signal when eight minutes have elapsed from the detection of the system halt. Further, the recovery system includes a selector consisting of a one-bit register for storing an initial value for enabling operation of the fault detector at the start of the computer system, the selector being connected to the system bus and changing its initial value in response to a BIOS program from the system bus to disable the operation of the fault detector. The computer system is set to save the data processed in an application program in response to the SMI signal.

System for automatic fault detection and recovery in a computer system

A control system for an automatic shutdown of a power supply constructed with a switching mode power supply (SMPS) receiving an AC voltage and converting the AC voltage into a DC voltage; a main board receiving the DC voltage output from the switching mode power supply; and a control circuit controlling and maintaining the supply of power from the switching mode power supply to the main board until a shutdown process is performed when power is turned OFF, wherein the control system enables the automatic shutdown of a power supply while preventing a file or a system from being damaged by automatically cutting off power after performing the shutdown process by the power control system even though the power switch is turned OFF due to the carelessness of the user or an external factor.

Control system and method for automatic shutdown of a power supply

A cache line replacing apparatus for use in a computer system having a central processing unit (CPU), a main memory and a cache memory, in which a cache line information of a CPU/cache bus is written-back into the main memory, and desired cache line information is read from the main memory to a memory bus to transmit the read cache line information to the CPU/cache bus, the cache line replacing apparatus including a first storage unit in which write-back data of the CPU/cache bus is stored, a second storage unit in which data which is read from the main memory to the memory bus is stored, a register for increasing a count value thereof when data is stored in the second storage means and decreasing the count value when the data is read from the second storage means, and a multiplexer for selectively transmitting the data stored in the second storage means to the CPU/cache bus or transmitting the data of the memory bus to the CPU/cache bus, according to the count value of the register. Accordingly, the time delay due to the write-back buffering can be avoided and the CPU can read the data without the loss of the memory bandwidth.

Growing community of inventors

Seoul, South Korea

Jee-Kyoung Park