Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Jee-Hoon Han

Young-Woo Park

Dong-Sik Lee

Jang-Hyun You

Tae-Yong Kim

Jae-Hoon Jang

Young-Hwan Son

Dong-Hwa Kwak

Jong-Hoon Na

Jong-Min Lee

Sung-Hoi Hur

Jong-Man Kim

Jae-Kwan Park

Su-Jin Park

Jake Kim

Byong-Gon Lee

Ho-Jun Seong

Maeng-Eun Lee

Seon-Hong Lee

Young-Woong Kwon

Hee-Sung Choi

Sang-Ick Joo

Sung-Hun Lee

Seong Soon Cho

Nam-su Lim

Byung-jun Hwang

So-wi Jin

Ki-Soo Lee

Seok-Jung Yun

Jee-Won Kang

Yong-Won Chung

A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Vertical non-volatile memory device with high aspect ratio

Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Vertical memory devices including stacked conductive lines and methods of manufacturing the same

Vertical non-volatile memory device having channel-accomodating opening formed of etch stop region in lower stack layers

A secondary battery and a method of manufacturing the same are disclosed. In one aspect, the method includes preparing an electrode assembly comprising a positive electrode plate, a negative electrode plate, and a separator interposed therebetween. The method also includes freezing the electrode assembly after the electrode assembly is filled with an electrolyte solution, dipping the frozen electrode assembly in a liquid polymer material, retrieving the dipped electrode assembly from the liquid polymer material, and curing an external surface of the electrode assembly.

Secondary battery including polymer material layer and method of manufacturing the same, having a case seamlessly formed as a single body

A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

Method of fabricating flash memory device

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width.

Semiconductor devices and methods of manufacturing the same

A secondary battery is disclosed. In one aspect, the battery includes an electrode assembly including i) a positive electrode plate on which a positive active material is formed, ii) a negative electrode plate on which a negative active material is formed, and iii) a separator separating the positive and negative electrode plates. The battery also includes a can accommodating the electrode assembly, wherein the can has an inner surface facing the electrode assembly, an inner active material layer formed on the inner surface of the can and a securing layer covering the inner active material layer.

Secondary battery

A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.

Semiconductor device and method of fabricating the same

A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Methods of fabricating nonvolatile memory devices including voids between active regions and related devices

A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

NAND flash memory device

Method of fabricating a nonvolatile memory device

Methods of forming memory devices are provided. The methods may include forming a pre-stacked gate structure including a lower structure and a first polysilicon pattern on the substrate. The methods may also include forming an insulation layer covering the pre-stacked gate structure. The methods may further include forming a trench in the insulation layer by removing a portion of the first polysilicon pattern. The methods may additionally include forming a metal film pattern in the trench on the first polysilicon pattern. The methods may also include forming a first metal silicide pattern by performing a first thermal treatment on the first polysilicon pattern and the metal film pattern. The methods may further include forming a second polysilicon pattern in the trench. The methods may additionally include forming a second metal silicide pattern by performing a second thermal treatment on the second polysilicon pattern and the first metal silicide pattern.

Methods of fabricating semiconductor memory devices

A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.

NAND flash memory device having a contact for controlling a well potential

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Hwaseong-si, South Korea

Jee-Hoon Han