Intel Corporation

Other

Jed D Griffin

Jerry G Jex

Arnaud J Forestier

Kersi H Vakil

Abhimanyu Kolla

Nasser A Kurd

Chee How Lim

Keith M Self

Ernest Khaw

Kifah M Muraweh

Brett A Prince

Sivakumar Radhakrishnan

Scott R Rushford

Michael J Wiznerowicz

Isaac P Abraham

David R Johnson

David J Hotz

David Peart

Kapilan Maheswaran

Kersi Vakil

Fast phase coordinating systems and methods are disclosed. An example system includes a phase locator configured to detect a first phase of a reference signal and a first phase of a coordinating signal after the first phase of the reference signal. An integrator is configured to integrate from the first phase of the reference signal to a location phase of the coordinating signal and integrate oppositely from the first phase of the coordinating signal to a time-shifted phase of the reference signal and output the result. A control function is configured to shift the phase of the coordinating signal in response to output from the integrator.

Phase coordinating systems and methods

In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Transmitters providing cycle encoded signals

Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Receivers for cycle encoded signals

Embodiments of the present invention are directed to a dual-reference delay-locked loop that includes a first delay element that delays a clock signal. The rising phase and the falling phase of the delayed clock signal are used as a first and a second reference phases, respectively, for a phase detector. A second delay element delays the first reference signal with a tracking phase that centers between the two reference phases. The phase detector detects a difference between the average of the reference phases and the tracking or resultant phase and outputs a difference signal that biases the delay elements to slew to the left or the right so that the resultant phase is centered between the reference phases corresponding to the rising and falling edges of the incoming clock.

Dual-reference delay-locked loop (DLL)

A system may include biasing of diodes of a temperature sensor disposed in an integrated circuit die using a current from an off-die current source, generation of a voltage based on the current and a temperature of the integrated circuit die, and determination of a first temperature based on the voltage. Such a system may further include amplification of the voltage using an oscillator and a chopper stabilizer, determination of a first amplified voltage associated with a first state of the oscillator and a second amplified voltage associated with a second state of the oscillator, and determination of a third voltage based on the first amplified voltage and the second amplified voltage, wherein determination of the first temperature based on the voltage comprises determination of the first temperature based on the third voltage.

System to calibrate on-die temperature sensor

Thermal control for a controller in a data processing environment is described. In one embodiment, the invention includes detecting a temperature of a semiconductor device at a thermal sensor on the semiconductor device, comparing the detected temperature to a threshold, and generating a high interrupt if the temperature is above the threshold and a low interrupt if the temperature is below the threshold.

On-die temperature monitoring in semiconductor devices to limit activity overload

In some embodiments, a transmitter includes first encoding controlled frequency output circuitry to creates a magnitude encoded controlled frequency signal (CFS) and second encoding controlled frequency output circuitry to create a complementary a magnitude encoded controlled frequency signal (CCFS). Other embodiments are described and claimed.

Controlled frequency signals

In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Receivers for controlled frequency signals

An output stage for a differential amplifier is presented. If the differential amplifier is a matched current differential amplifier where the non-inverted and inverted differentials have the same current, the output stages of the present invention may provide optimum gain to the differentials in a single output voltage.

Differential amplifier output stage

In one embodiment of the invention, an update circuit having a bus driver to drive a bus dynamically receives an update compensation code. The bus driver receives data at a data clock signal. The update compensation code controls impedance matching at the bus driver according to the data. A code generator generates the update compensation code at a base clock signal. The base clock signal is synchronized with the data clock signal. The base clock signal has an update interval and a quiet interval. A distribution ring interface distributes the update compensation code to the update circuit synchronously with the base clock signal.

Dynamically updating impedance compensation code for input and output drivers

A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

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Forest Grove, OR, United States of America

Jed D Griffin