International Business Machines Corporation

Globalfoundries Inc.

Jds Uniphase Corporation

Minnesota Mining and Manufacturing Company

Agilent Technologies, Inc.

Lexmark International, Inc.

Avago Technologies General IP Pte, Ltd.

Jeannine Madelyn Trewhella

Mitchell S Cohen

Glen Walden Johnson

Modest M Oprysko

Guy M Cohen

Steven Alan Cordes

William K Hogan

David Peter Gaio

Joanna Rosner

Daniel Michael Kuchta

Mark B Ritter

Michael Frank Cina

Russell Alan Budd

Fuad Elias Doany

Jeffrey Alan Kash

Sherif Ahmed Goma

Stephen Louis Spanoudis

Paul William Coteus

Kerry Bernstein

Daniel Joseph Friedman

Philip George Emma

Ruchir Puri

Michael R Tan

Albert M Young

Steven Paul Ostrander

Roderick Alan Augur

Nicholas A Lee

Jeremy Daniel Schaub

Nicholas A Polomoff

Ibrahim M Elfadel

Sylvain E Ouimet

Lei Shan

Punit P Chiniwalla

Dennis L Karst

Marco Gauvin

John Andrew Guckenberger

Garry Trott

Andre Lacerte

Stephane Tremblay

Kevin M Boyd

Guy A Cohen

John Ulrich Knickerbocker

Jeffrey Donald Gelorme

James L Speidell

Sudipta Kumar Ray

Phillip Duane Isaacs

Gary Richard Trott

Robert Fox

Blake G Fitch

Ronald Pete Luijten

Bunsen Fan

Robert S Germain

Michael James Cordes

William T Devine

Miles Frank Swain

Dianne L Lacey

Donis G Flagello

Robert J Fox, Iii

Patrick E McKnite

Albert Speth

Joseph P Zinter

Gary R Trott

A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

Crack stop with overlapping vias

One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer.

Crack-stop structure for an IC product and methods of making such a crack-stop structure

A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Processing for overcoming extreme topography

A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

Wafer level I/O test, repair and/or customization enabled by I/O layer

For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.

Interconnecting (mapping) a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array

A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

Wafer level I/O test and repair enabled by I/O layer

Apparatus and methods for packaging optical communication devices include optical bench structures, such as silicon-optical benches (SiOB). An optical communications apparatus includes an optical bench comprising a substrate having an electrical turning via formed therein. An optoelectronic (OE) chip and integrated circuit (IC) chip are mounted on the optical bench and electrically connected using the electrical turning via. The electrical turning via extends in directions both perpendicular and transverse to a surface of the substrate such that the OE chip and IC chip can be mounted on perpendicular surfaces of the optical bench in close proximity and electrically connected using the electrical turning via. More specifically, the OE chip and IC chip are mounted on the optical bench such that a light-emitting or light-detecting surface of the OE chip is substantially perpendicular to a surface of the IC chip having contacts, and such that optical transmission lines that are mounted parallel to the substrate surface can be directly coupled to the OE chip.

Apparatus and methods for integrally packaging optoelectronic devices, IC chips and optical transmission lines

At least one optical waveguide is supported on a substrate and has a plurality of key apertures formed in a complaint element thereof. An optoelectronic device such as a vertical cavity surface emitting laser (VCSEL) has a plurality of projections that register with corresponding key apertures to position the optoelectronic device in a predetermined alignment relative to the optical waveguide.

Optical assembly with optoelectronic device alignment

An information processing system, includes several processors, each having at least one optical fiber input and at least one optical fiber output; a controller having an optical fiber input and at least one fiber output; fibers, bundled for transmitting information; and a fiber bundle redriver, coupled to the controller, having an input channel and an output channel, for simultaneously redriving an optical signal received from any selected one of the plurality of input fibers onto substantially all of the plurality of output fibers. The fiber output of each of the plurality of processors and the at least one fiber output of the controller are respectively is coupled to the input channel of the fiber bundle redriver, and the at least one fiber input of each of said plurality of processors and the fiber input of the controller are respectively coupled to the output channel of the fiber bundle redriver.

Method and apparatus for a scalable parallel computer based on optical fiber broadcast

An integrated circuit arrangement or package includes a set of contact pads arranged in a pattern and a multi-layer conductive structure, which electrically connects the set of contact pads to at least one signal line. The conductive structure provides impedance matching between the pads and the at least one signal line.

Via and via landing structures for smoothing transitions in multi-layer substrates

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Peekskill, NY, United States of America

Jeannine Madelyn Trewhella