International Business Machines Corporation

Jeannie H Panner

Paul Steven Zuchowski

Michael Richard Ouellette

Scott Whitney Gould

William John Livingstone

Thomas R Bednar

Frank O Distler

Paul E Dunn

Janice M Adams

Mark F Ollive

Laura R Darden

Bruce D Raymond

Steven H Voldman

Peter Anton Habitz

Douglas Willard Stout

Patrick Edward Perry

Peter Claude Elmendorf

Harry John Beatty, Iii

Erich C Schanzenbach

Andrew D Huber

William F Pokorny

Bruce Cowan

Bijan Salimi

James J Engel

Daniel Joseph Mainiero

Lansing Dunn Pickup

Philip S Homsinger

Dora R Pealer

Donald L Hubbard

Michael Timothy Trick

Debra K Korejwa

A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Automation of fuse compression for an ASIC design system

Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

A method for design auditing by automating ways of auditing data produced by process steps is disclosed. The invention automates the process of auditing to account for complex methodology conditions. It also automates auditing of values of data produced by methodology steps. The invention provides a means of grouping task and information within a program and of preserving parent-child relationships.

Automated audit methodology for design

A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Method of automated design and checking for ESD robustness

It is, therefore, an object of the present invention to provide a structure and method of blowing fuses in a semiconductor chip that includes creating a design for the chip using a library, generating test data from the design, extracting the fuse related information from the design to prepare a fuse blow table, building the chip with the design data, testing the chip to produce failed data, comparing the fuse blow table to the failed data to determine the fuse blow location data, and blowing the selected fuses based on the fuse blow location data. The extraction method can include creating a fuse map file based upon a correlation between physical pin locations on the chip and different fuse macros within the design, wherein an order of fuses within the fuse blow table matches an order of fuses within the fuse map file.

Automated fuse blow software system

A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

Three dimensional track-based parasitic extraction

A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

Redundant vias

A method for verifying that an integrated circuit design tool kit has not been modified in an unauthorized manner is accomplished by providing a verification procedure that, when an executable subrule of the tool kit has been selected to be part of the rule system, the executable subrule reads a table of time stamps. This table of time stamps and a key are provided, as representative data, to an authentication subrule by the executable subrule. The executable subrule and the authentication subrule perform an authentication check algorithm upon the representative data to produce remotely and locally checked data respectively. The executable subrule then provides the locally checked data to the authentication subrule which compares the locally checked data with the remotely checked data. When a match occurs between the data, the authentication subrule indicates that the executable subrule has not been modified in an unauthorized manner. When the locally checked data does not match the remotely checked data, the authentication subrule indicates that an unauthorized modification has occurred.

Method for building and verifying authenticity of a rule system

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Underhill, VT, United States of America

Jeannie H Panner