Sun Microsystems, Inc.

Cadence Design Systems, Inc.

Jeannette Sutherland

Amit Dhuria

Robert E Mains

Matthew J Amatangelo

Naresh Kumar

Prashant Sethia

Arvind Nembili Veeravalli

Shervin Hojat

Saulius Kersulis

Shashank Tripathi

Sarath Jayalath Kirihennedige

Embodiments included herein are directed towards a method for comparing constraint sets. The embodiments may include determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set. The embodiments may further include creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set. The embodiments may also include determining, using the at least one processor, at least one of: a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and an equivalent path exception corresponding to the at least one endpoint.

System and method for comparing circuit design constraint sets

A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

High performance static timing analysis system and method for input/output interfaces

Broadly speaking, a method is provided for evaluating nets in a crosstalk noise analysis. More specifically, a method is provided for evaluating timing window overlap between a pair of nets. The method includes selecting one timing window from each net of the pair of nets for analysis. The method further includes analyzing characteristics of the timing windows selected from the pair of nets to identify a timing window overlap presence, wherein the timing window overlap presence can exist between any two timing windows associated with each net of the pair of nets, respectively.

Method for evaluating nets in crosstalk noise analysis

Given two synchronous clocks which transact data from a transmitter element to a receiver element which are analyzed by static timing, the interval between the transmitting data launch clock edge and the receiving capture clock edge is adjusted from the clock waveforms provided in order to represent the worst case slack situation between these two clocks over time. The amount of this adjustment is determined without unrolling (enumerating) all possible launch/capture pairs for these clocks. The greatest common divisor (GCD) of a transmit clock frequency and a receive clock frequency is determined. An effective phase shift is determined by performing a MOD operation between the GCD and an offset of the transmitter and receiver clocks. An algorithm uses the GCD and effective phase shift to determine a launch/capture interval that corresponds to a critical slack condition.

Determining cycle adjustments for static timing analysis of multifrequency circuits

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Jeannette Sutherland