Intersil Americas Inc.

Harris Corporation

Jeanne Marie McNamara

Donald Frank Hemmenway

Patrick Anthony Begley

Anthony L Rivoli

John T Gasner

George S Bajor

Dustin Alexander Woodbury

Michael Sean Carmody

Phillip J Benzel

Helen Hongwei Li

Joy Ellen Jones

Lawrence G Pearce

John J Hackenberg

David H Leebrick

Deborah K Rodriguez

Choong S Rhee

A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter.

Devices including bond pad having protective sidewall seal

A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.

Protecting bond pad for subsequent processing

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches . Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

Wafer trench article and process

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Process of forming trench isolation device

An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Programmable element in barrier metal device

To planarize an oxide-filled shallow trench-isolated semiconductor architecture, a composite photoresist sacrificial layer is initially formed on the oxide-filled structure. The composite photoresist layer contains photoresist plugs which are reflowed to fill depressions in the oxide fill layer overlying the trench, and an overlying photoresist layer which effectively planarizes the depression-filled trench oxide layer. Respective photoresist and oxide selective etching chemistries are then successively applied to first etch the composite sacrificial photoresist layer and then etch the trench fill oxide layer down to the surface of an etch stop polysilicon layer. Since the thickness of the polysilicon etch stop layer is initially formed so as to extend above the mesa layer of the trench-isolated semiconductor structure by a relatively nominal height, after planarization, the top surface of the trench fill oxide layer still extends above the surface of the mesa to prevent shorting of a subsequently formed polysilicon gate layer with underlying mesa material, while being sufficiently low enough to avoid sidewall stringer formation.

Growing community of inventors

Palm Bay, FL, United States of America

Jeanne Marie McNamara