Intel Corporation

Jeanne Luce

Ebony L Mays

Michael L Hattendorf

Byron Ho

Erica J Thompson

Christopher P Auth

Sameer S Pradhan

Chun-Kuo Huang

Ritesh Jhaveri

Dennis G Hanken

Sang-Won Park

Aravind S Killampalli

Jay P Gupta

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

Fin end plug structures for advanced integrated circuit structure fabrication

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

Interlayer dielectric for non-planar transistors

Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.

Semiconductor device having fin-end stress-inducing features

A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

Dielectric gap-fill material deposition

Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.

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Hillsboro, OR, United States of America

Jeanne Luce