Advanced Micro Devices Corporation

Other

Spansion Llc.

Fasl LLC

Jean Y Yang

Mark T Ramsbey

Hidehiko Shiraiwa

Tazrien Kamal

Minh Van Ngo

Yider Wu

Arvind Halliyal

Emmanuil Lingunis

Jaeyong Park

Angela Tai Hui

Kouros Ghandehari

Rinji Sugino

Yu Nan Sun

Ning Cheng

Jeffrey Allan Shields

Cyrus E Tabery

Michael Allen Van Buskirk

Narbeh Derhacobian

Ravi S Sunkavalli

David Michael Rogers

Janet S Wang

Amir Hossein Jafarpour

Inkuk Kang

Hirokazu Tokuno

Weidong Qian

Ian Dudley

Scott Allan Bell

Tuan Duc Pham

Khoi A Phan

Lu You

Mark W Randolph

Chi K Chang

Wei Zheng

Yi He

Zhizheng Liu

Khanh Q Tran

Meng Ding

Ming Sang Kwan

Krishnashree Achuthan

Fred T K Cheung

Shenqing Fang

Kuo-Tung Chang

Richard J Huang

Yi Ma

Dawn M Hopper

Simon S Chan

Christopher A Spence

Alexander H Nickel

Youseok Suh

Jiang Li

Hieu T Pham

Che-Hoo Ng

Jeff P Erhardt

Cinti Xiaohua Chen

Patrick K Cheung

Jusuke Ogura

David H Matsumoto

Michael Brennan

Eunha Kim

Joerg Reiss

Terri Jo Kitson

Vidyut Gopal

Clarence B Ferguson

Jeremy Wahl

Paula Rao

Mark E Ramsbey

Ravi Sunkavalli

Janet Wang

Dog vest with pockets

A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

Memory manufacturing process with bitline isolation

A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Strapping contact for charge protection

A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

3-D integrated circuit system and method

A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.

Method for improved planarization in semiconductor devices

A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

Bit line implant

A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.

Void free interlayer dielectric

A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by providing a semiconductor substrate having a silicon surface; forming a first oxide layer on the silicon surface; depositing a silicon nitride layer on the first oxide layer; and forming a top oxide layer on the silicon nitride layer, wherein the top oxide layer is formed by an in-situ steam generation oxidation of a surface of the silicon nitride layer. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate FLASH memory device including an ONO structure.

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.

UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing

Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.

Disposable hard mask for memory bitline scaling

A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.

Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.

Flash memory cell with UV protective layer

A SONOS flash memory device, including a semiconductor substrate; an ONO structure formed on the semiconductor substrate, the ONO structure including a bottom oxide layer, a dielectric charge storage layer and a top oxide layer, the bottom oxide layer having a super-stoichiometric oxygen content and an oxygen vacancy content of about 10/cmor less, wherein the bottom oxide layer exhibits a reduced charge leakage relative to a bottom oxide layer having a stoichiometric or sub-stoichiometric oxygen content and a greater number of oxygen vacancies. In one embodiment, the bottom oxide layer has an oxygen vacancy content of substantially zero.

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

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Sunnyvale, CA, United States of America

Jean Y Yang