Nxp Usa, Inc.

Freescale Semiconductor,inc.

Jean-Stephane Vigier

Cristian Pavao Moreira

Didier Salle

Julien Orlando

Dominique Delbecq

Cristian Pavao-Moreira

Matthis Bouchayer

Birama Goumballa

Andres Barrilado Gonzalez

Olivier Vincent Doaré

Pierre Pascal Savary

Laurent Gauthier

Lionel Geynet

Olivier Doaré

A communication unit includes a plurality of cascaded devices that include at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device and at least one slave device each include: a demodulator circuit configured to receive a distributed reference clock signal and re-create a system clock signal therefrom; a clock generation circuit that includes an internally-generated reference phase locked loop configured to receive the re-created system clock signal to create a master-slave clock signal; and an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use a same master-slave clock signal to align respective sampling instants between each ADC of the at least one master device and at least one slave device.

Communication unit, integrated circuits and method for clock and data synchronization

A communication unit () is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit () configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (); and transmit the modulated master-slave clock signal () to the at least one slave device. The at least one slave device comprises a demodulator circuit () configured to: receive and demodulate the modulated master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit and method for clock distribution and synchronization

A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

Boosted return time for fast chirp PLL and calibration method

A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

Phase preset for fast chirp PLL

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device () and at least one slave device () configured in a master-slave arrangement. The at least one master device () and at least one slave device () each comprise: an analog-to-digital converter, ADC, () configured to use a same re-created system clock signal () to align respective sampling instants between each ADC (). The at least one master device () comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (), configured to output a system clock signal (); and a modulator circuit () coupled to the clock generation circuit and configured to receive and distribute the system clock signal (). The at least one master device () and at least one slave device () each comprise: a demodulator circuit () configured to receive the distributed system clock signal () and re-create therefrom a synchronized system clock signal () used by a respective ADC, () of each of the the master device () and at least one slave device ().

An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.

Duty cycle monitor circuit and method for duty cycle monitoring

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit () configured to: receive a modulated embedded master-slave clock signal () that comprises a system clock signal () with an embedded frame start signal (); demodulate the modulated embedded master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit, integrated circuit and method for clock distribution and synchronization

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit () coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (); and transmit the modulated embedded master-slave clock signal () to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device () and at least one slave device ().

An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable. By the arrangement of unitary varactors a very small step size is achieved for providing a high resolution of frequency of a digitally controlled oscillator.

Capacitive arrangement for frequency synthesizers

An electronic device has a calibration arrangement for controlling a frequency characteristic of a PLL circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. A modulation unit has a modulation input for receiving a modulation signal and generates the oscillator modulation signal and the divisor such that modulation generates a predefined change of the output frequency and a change of the divisor proportional to said predefined change. The calibration arrangement receives the phase difference signal, and has a ripple detector for providing a detector output signal by detecting a ripple on the phase difference signal correlated to edges in the modulation signal. A calibration control unit adjusts the oscillator modulation signal based on the detector output signal such that the ripple is reduced.

Calibration arrangement for frequency synthesizers

An integrated circuit device comprises tuning signal circuitry for generating a tuning signal for calibrating a voltage controlled oscillator (VCO). The tuning signal circuitry is arranged to receive a target voltage signal that is representative of a target voltage across at least one passive element within a resonant tank circuit of a VCO that is being calibrated, generate a VCO simulation signal representative of an average voltage difference across at least one active component of the VCO that is being calibrated, and output a tuning signal based at least partly on the received target voltage signal and the generated VCO simulation signal.

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Mondonville, France

Jean-Stephane Vigier