Nxp B.v.

Jean-Robert Tourret

Vincent Fillatre

Frederic Darthenay

Franck Goussin

Vincent Geffroy

A bias circuit for generating a virtual reference voltage is described. The bias circuit may bias a switching device configured to switch a switching device output between a first and second supply voltage. The bias circuit includes a bias stage coupled between the first supply voltage rail and the second supply voltage rail. The bias stage has a bias stage output configured to output a virtual reference voltage value having a value between the first and second supply voltage. The bias circuit further includes a voltage follower coupled to the bias stage. The voltage follower is configured to output the virtual reference voltage. The bias circuit further includes a first charge pump coupled to the voltage follower output; and at least one of a second charge pump coupled to the bias stage voltage output, and a switchable buffer coupled to the bias stage voltage output and the voltage follower output.

Bias circuit

A plurality of chained clock dividers provides a plurality of generated clocks generated from a root clock. Each clock divider provides a generated clock having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock. Clock gating circuitry selectively gates the generated clocks based on a clock ready signal and provides the generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the generated clocks are ready. A delay circuit has an inverted clock input configured to receive a final generated clock. The delay circuit provides a trigger output in response to a falling edge of the final generated clock. A set of synchronization flip flops receives a clock enable signal and the trigger output and provides the clock ready indicator based on the clock enable signal and the trigger output.

Clock control in a system on a chip (SoC)

A touch screen is disclosed having a length and a height, and comprising interspaced and galvanically isolated first and second arrays of touch pads; wherein the first array of touch pads comprises a plurality of first strings of series-connected touch pads, each first string forming a drive line and extending in a first general direction; wherein the second array of touch pads comprises a plurality of second strings of series-connected touch pads, each second string forming a read line and extending in a second general direction, different to said first general direction; wherein the first general direction and the second general direction are each different from the length direction; and wherein the touch screen is configured for capacitive-based sensing which may be based on a change in a mutual capacitance between individual ones of the drive lines and individual ones of the read lines.

Capacitive touch screens

A touch panel system that includes drivers for providing detection signals on a first plurality of electrodes of a touch panel where each detection signal includes one or more frequency signal components with each frequency signal component having a frequency and a phase offset. The detection signals includes at least three phase offsets for at least one frequency of the frequency signal components. Each detection signal has a unique frequency-phase offset combination of the one or more frequency signal components. The unique combinations allow for the determination of a touch at specific locations on the panel by sensing signals on a second set of electrodes.

Tough panel location detection with different frequency-phase offset combinations of electrode signals

A low drop out, LDO, voltage regulator circuit is that includes a high gain amplifier configured to receive a current biasing signal and arranged to regulate the voltage supply signal and output a regulated voltage supply signal. A regulation adjustment circuit is operably coupled to an output of the high gain amplifier and includes a comparator configured to compare the output regulated voltage supply signal with a threshold, wherein an output of the comparator is configured to perform one of: (i) supply a dynamic current boost to the LDO current biasing signal, in response to the regulated voltage supply signal voltage dropping below the threshold; (ii) activate a dynamic current pull down circuit to reduce an over voltage output of the LDO voltage regulator circuit in response to the regulated voltage supply signal voltage exceeding the threshold.

Voltage regulator circuit and method therefor

An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

Circuit for detecting phase shift applied to an RF signal

An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronization signal divider for distributing a synchronization signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronization signal divider.

RF circuit

A local oscillator signal generation circuit for a frequency divider circuit is disclosed. The local oscillator signal generation circuit includes a delay device adapted to delay a data signal according to a control signal, a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so that the data signal is stable when it is sampled by the data flip-flop. A local oscillator signal is derived from the output of the data flip-flop.

Local oscillator signal generation

Digital spur reduction in which spurs are kept outside selected channels of interest. An integrated radiofrequency transceiver circuit has digital and analogue components, the circuit includes a radiofrequency signal receiver having a local oscillator signal generator configured to provide a local oscillator signal at a frequency fand a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency ffor operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

RF digital spur reduction

Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fand a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency ffor operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

The present invention relates to a low-voltage self-calibrated peak detector (). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (), the peak detection is made accurate whatever temperature, process or mismatch spreads. Its input bandwidth can be as high as the bandwidth of an operational amplifier of unity gain. In a rail-to-rail configuration, it can be implemented into a fully differential low-voltage self-calibrated CMOS peak detector (), which can have a very high conversion gain (&#x3b1;) and a very high input signal dynamic ranging.

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Cormelles le Royal, France

Jean-Robert Tourret