Centre National De La Recherche Scientifique

Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Jean-Pierre Laur

Jean-Louis Sanchez

Jean Jalade

Patrick Austin

Marie Breil

Eric Bernier

Olivier Causse

Henri Foch

Mathieu Roy

Jean-Baptiste Quoirin

Hedi Hakim

The invention concerns the control of thyristor-type semiconductor power components (Sw) powered by an alternating current network (VS). The control signal is a pulse (Ie). It is stored in the form of magnetic induction (B), positive or negative, in a core (T) made of ferromagnetic material. At each current alternation of the network, the interrogation of the magnetic state of the strand results in the presence, or not, of a control signal on the power device (Sw).

Method and pulse-control circuit for a power component

The invention concerns an anode voltage sensor of a vertical power component selected from the group consisting of components called thyristor, MOS, IGBT, PMCT, EST, BRT transistor, MOS thyristor, turn-off MOS thyristor, formed by a lightly doped N-type substrate ( ) whereof the rear surface ( ) having a metallizing coat corresponds to the component anode. Said sensor comprises, on the front surface side, a substrate zone ( ) surrounded at least partly by a P-type region with low potential in front of an anode potential, said zone ( ) being coated with a metallizing coat (M) in ohmic contact with it, whereon is provided an image of the anode voltage.

Anode voltage sensor of a vertical power component and use for protecting against short circuits

The invention concerns a variable capacitance capacitor comprising a periodic structure of raised zones ( ) separated by recesses ( ) formed in a type N semiconductor substrate ( ). The walls of the raised zones and the base of the recesses are coated with a conductive layer ( ). The substrate is connected to a first terminal (A) of the capacitor and the conductive layer to a second terminal (B) of the capacitor. At least the base of the recesses or the side of the raised zones comprises type P regions ( ), the pitch of the raised parts being selected so that the space charging zones linked to the type P regions are joined when the voltage difference between said terminals exceeds a predetermined threshold. The zones not comprising type P regions are coated with an insulant ( ) and a highly doped N region ( ) is formed beneath the insulant.

Variable-capacitance capacitor

A peripheral structure for a monolithic power device, preferably planar, includes front and rear surfaces, connected respectively to a cathode and an anode, two junctions respectively reverse-biased and forward-biased when a direct and adjacent voltage is respectively applied to the two surfaces and at least an insulating box connecting the front and rear surfaces. The structure is such that when a direct voltage or a reverse voltage is applied, generating equipotential voltage lines, the insulating box enables to distribute the equipotential lines in the substrate.

Peripheral structure for monolithic power device

A monolithic power switch with a controlled di/dt including the parallel assembly of a MOS or IGBT type component with a thyristor type component, including means for inhibiting the thyristor type component during the closing phase of the switch, which is ensured by the IGBT type component. The IGBT type component has a vertical multicell structure and the component of thyristor type has a vertical monocell structure.

Power switch with a controlled DI/DT

The present invention relates to a component forming a normally on dual thyristor, which can be turned off by a voltage pulse on the control electrode, including a thyristor, a first depletion MOS transistor, the gate of which is connected to the source, connected between the anode gate and the cathode of the thyristor, and a second enhancement MOS transistor, the gate of which is connected to a control terminal.

Normally conducting dual thyristor

A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.

Growing community of inventors

Albi, France

Jean-Pierre Laur